Simon McIntosh-Smith Follow @simonmcs
- Head of Microelectronics Research Group
- Professor of High Performance Computing
- Expert in performance portability techniques and application-based fault tolerant computing (ABFT)
- PI of the first Intel Parallel Computing Center (IPCC) in the UK
- Contributor to both the OpenCL and OpenMP parallel programming standards
- Major contributor to the Mantevo mini-app suite of codes, specifically CloverLeaf and TeaLeaf
- Founder of the International Workshop on OpenCL (IWOCL)
- Member of the EPSRC Archer national supercomputer design team
- Vice chair of the University of Bristol's HPC exec
- External examiner for EPCC's HPC and big data masters degrees
- Member of EPSRC's new Research Infrastructure Strategic Advisory Team (2011-2015)
- Member of EPSRC's resource allocation panel (RAP) for HECToR, the UK's national supercomputer resource
- Regular member of the programme committee for IEEE/ACM SuperComputing and ISC
Fifteen years semiconductor industry experience in many-core microprocessor architecture design at Inmos, STMicroelectronics, Pixelfusion and ClearSpeed
- As a founder at ClearSpeed I had various senior technical roles between 2002 and 2008 including VP of Applications and Director of Architecture. I co-developed the architecture of our record-breaking many-core processors, including the 192 core CSX700, 96 core CSX600, and 64 core CS301 prototype
- At Pixelfusion I was a microprocessor architect and low-level GPU driver developer for our innovative 1,536-core graphics processor, the F150. This was the first true GPGPU and also included the world's fastest Rambus implementation at the time (4 channels delivering 6.4 GBytes/s, a lot in 2000!) and the first commercial implementation of an Arc core. It also pioneered using redundant cores to tolerate manufacturing defects in many-core devices.
- Graduated as valedictorian with a first class degree in Computer Science from Cardiff University
- Performance portablity
- Application-based fault tolerance (ABFT)
- New algorithms for novel architectures
- Heterogeneous, many-core processor architectures, including GPUs, Xeon Phi, FPGAs, DSPs etc.
- Scaling applications to run on millions of cores (Exascale computing)
Workshops and Tutorials
- I run many tutorials and workshops in parallel programming, especially using OpenCL and OpenMP. I run these courses for both industrial partners and academic institutions. Courses can be anything from a 1/2 day introduction, to a 3-day advanced workshop. Get in touch if you're interested in having such a course run for your group.
- COMSM0109: Advanced Computer Architecture with David May. This course enables you to really understand how processors work and how best to exploit modern processor features from software.
- COMS30004: High Performance Computing. This course takes you through the theory and hands-on practise of high performance computing, focusing on parallel processing models, and applying these to the latest cutting edge computer architectures.
- COMS12900: HiTec Enterprise (Unit director) - first year introductory course to innovation and entrepreneurship. This course will equip you with highly marketable skills that will prove valuable through your remaining time in Bristol, and beyond.
- COMSM0306: Individual project business plan (Unit director) - fourth year course. Advanced topics on how real companies work, innovation, entrepreneurship and transferrable skills. This is one of the top courses of its kind anywhere in the world (we know, we did the benchmarking), and will make you extremely marketable. The skills you learn here will be incredibly valuable throughout your entire career, no matter what kind of roles you choose.