Publications

Here you can find a list of publications by the members of the μ group. This may include publications made prior to the formation of the group and will also include past members.

1. 2012

   • Coverage Directed Test Generation Automated by Machine Learning

     ACM Transactions on Design Automation of Electronic Systems (TODAES)

     Ioannides, C & Eder, KI.

   • Energy Efficient HPC Software: Learning from Embedded Systems Development

     SIAM Conference on Parallel Processing for Scientific Computing

     Kerrison, SP, Eder, KI & McIntosh-Smith, SN.

   • Video Super-resolution Using Generalized Gaussian Markov Random Fields

     IEEE Signal Processing Letters

     Chen, J, Nunez-Yanez, JL & Achim, AM.

   • Benchmarking energy efficiency, power costs and carbon emissions on heterogeneous systems

     The Computer Journal

     McIntosh-Smith, S, Wilson, T, Avila Ibarra, A, Crisp, J & Sessions, RB.

2. 2011

   • A Design-for-Verification Framework for a Configurable Performance-Critical Communication Interface

     Proceedings of the 9th International Conference on Formal Modeling and Analysis of Timed Systems, LNCS

     Abu Kharmeh, S, May, MD & Eder, KI.

   • Fast Distributed Process Creation with the XMOS XS1 Architecture

     Communicating Process Architectures 2011

     Hanlon, JW & Hollis, SJ.

   • A Routing-Aware ILS Design Technique

     IEEE Transactions on Very Large Scale Integration Systems

     Benerjee, S., Matthew, J. & Pradhan, DK.

   • Multi-standard reconfigurable motion estimation processor for hybrid video codecs

     IET Computers & Digital Techniques

     Nunez-Yanez, JL, Spiteri, T & Vafiadis, G.

   • Implementation and Evaluation of Skip-links: A Dynamically Reconfiguring Topology for Energy-efficient NoCs

     International Journal of Embedded and Real-Time Communication Systems (IJERTCS)

     Jackson, CR & Hollis, SJ.

   • Matrix codes for reliable and cost efficient memory chips

     IEEE Transactions on VLSI Systems

     Argyrides, C, Pradhan, DK & Kocak, T.

3. 2010

   • A Deadlock-free Routing Algorithm for Dynamically Reconfigurable Networks-on-Chip

     Microprocessors and Microsystems

     Jackson, CR & Hollis, SJ.

   • Dynamic generation of parallel computations

     The 2010 UK Electronics Forum

     Hanlon, JW & Hollis, SJ.

   • Skip-links: A Dynamically Reconfiguring Topology for Energy-efficient NoCs

     International Symposium on System-on-Chip 2010

     Jackson, CR & Hollis, SJ.

   • Skip the Analysis: Self-optimising Networks-on-Chip (Invited paper)

     Proc. International Symposium on Electronic System Design (ISED)

     Hollis, SJ & Jackson, CR.

   • Simplified Bit Parallel Systolic Multipliers for Special Class of GF(2m) with Testability

     IET Computers and Digital Techniques

     H. Rahaman, Jimson Mathew, A. Jabir & Dhiraj Pradhan.

   • Practical Experiences Constructing Working Virtual Machines

     Refinement Based Methods for the Construction of Dependable Systems

     Steve Wright.

   • Using Event-B to construct Instruction Set Architectures

     Formal Aspects of Computing

     Steve Wright & Kerstin Eder.

   • ULS: A Dual-Vth/High-K Nano-CMOS Universal Level Shifter for System-Level Power Management

     ACM Journal of Emerging Technologies in Computing (JETC)

     S.P. Mohanty & Dhiraj Pradhan.

   • P3 (Power-Performance-Process) Optimization of Nano-CMOS SRAM using Statistical DOE-ILP

     11th IEEE International Symposium on Quality Electronic Design (ISQED)

     G. Thakral, S. P. Mohanty & Dhiraj Pradhan.

   • A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM

     IEEE International Conference on VLSI Design (VLSID)

     G. Thakral, S. P. Mohanty & Dhiraj Pradhan.

   • Using a Formal Property Checker for Simulation Coverage Closure

     Design Automation Conference

     Tim Blackmore, David Halliwell, Phil Barker, Kerstin Eder & Naresh Ramaram.

   • Formal Analysis of a Programmable Performance-Critical Processor Communication Interface

     Proceedings of the 10th International Workshop on Automated Veri?cation of Critical Systems (AVoCS 2010)

     Abu Kharmeh, S, Kerstin Eder & David May.

   • A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM

     IEEE International Conference on VLSI Design (VLSID 10)

     G. Thakral, S. P. Mohanty, D. Ghai & Dhiraj Pradhan.

   • Efficient Fault Tolerant De Bruijn Based Design Approach for Sensor Networks

     4^th International Conference on Sensor Technologies and Applications, 2010. SENSORCOMM , Italy

     Anas Abu Taleb, Jimson Mathew & Dhiraj Pradhan.

   • Clustered De Bruijn Multi Layered Architectures for Sensor Networks

     Lecture notes in Computer Science

     Anas Abu Taleb, Jimson Mathew & Dhiraj Pradhan.

   • A Novel Fault Diagnosis Technique in Wireless Sensor Networks

     The International Journal On Advances in Networks and Services

     Anas Abu Taleb, Jimson Mathew & Dhiraj Pradhan.

   • Fault Diagnosis in Multi Layered De Bruijn Based Architectures for Sensor Networks

     6^th IEEE Int Workshop on Sensor Networks and Systems for Pervasive computing((PerSeNs 2010)

     Anas Abu Taleb, Jimson Mathew & Dhiraj Pradhan.

   • A Galois Field Based Logic Synthesis Approach with Testability

     IET Computers & Digital Techniques

     Jimson Mathew, A Jabir, A.K Singh, H.Rahaman & Dhiraj Pradhan.

   • Investigating the Impact of NBTI on Different Power Saving Cache Strategies

     To appear in the proceedings of IEEE International Conference, DATE, 2010, Germany

     Andrew Ricketts, Jawar Singh, Vijaykrishnan Narayanan & Dhiraj Pradhan.

   • Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn Graph

     IEEE Transactions on Very Large Scale Integration (VLSI) Systems

     M. Hosseinabady, R. Kakoee, Jimson Mathew & Dhiraj Pradhan.

   • DOE-ILP Based Simultaneous Power and Read Stability Optimization in Nano-CMOS SRAM

     Journal of Low Power Electronics

     S. Mohanty & Dhiraj Pradhan.

   • A Novel Si-Tunnel FET SRAM Design for Ultra Low-Power 0.3V VDD Application

     To appear in the proceedings of 15th Asia South Pacific Design Automation Conference (ASPDAC), January, Taipei, Taiwan, 2010

     Jawar Singh, K. Ramakrishnan , S. Mookerjea, S. Datta, V. Narayanan & Dhiraj Pradhan.

   • A DOE-ILP Assisted Conjugate-Gradient Approach for Power and Stability Optimization in High-?/Metal-Gate SRAM

     ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI)

     G. Thakral, S. P. Mohanty, D. Ghai & Dhiraj Pradhan.

   • Introduction to design techniques for energy harvesting

     ACM Journal on Emerging Technologies in Computing Systems

     Kocak, T & Pradhan, DK.

   • Differential patterning of neuronal, glial and neural progenitor cells on phosphorus-doped and UV irradiated diamond-like carbon

     Biomaterials

     Regan, EM, Uney, JB, Dick, AD, Zhang, Y, Nunez-Yanez, JL, McGeehan, JP, Claeyssens, F & Kelly, S.

4. 2009

   • Initialisation and Synchronisation for a Dynamic Topology Network-On-Chip Architecture

     Jackson, CR & Hollis, SJ.

   • When does Network-on-Chip Bypassing Make Sense?

     Proc. 22nd IEEE SoCC Conference

     Hollis, SJ & Jackson, CR.

   • Pulse Generation for On-chip Data Transmission

     Proc. 12th Euromicro DSD Conference on Digital System Design (DSD09)

     Hollis, SJ.

   • Real-time fluid simulation using discrete sine/cosine transforms

     I3D '09: Proceedings of the 2009 symposium on Interactive 3D graphics and games

     Benjamin Long & Erik Reinhard.

   • A Generic Instruction Set Architecture Model in Event-B for Early Design Space Exploration

     Fangfang Yuan & Kerstin Eder.

   • A novel error correction technique for adjacent errors

     10th European Conference on Radiation Effects on Components and Systems ? RADECS 2009

     Costas Argyrides, Pedro Reviriego, Juan A. Maestro & Dhiraj Pradhan.

   • Reliability Aware Yield Improvement Technique for Nanotechnology Based Circuits

     22nd annual symposium on Integrated circuits and system design SBCCI `09

     Costas Argyrides, Giorgos Dimosthenous, Carlos Lisboa, Luigi Carro & Dhiraj Pradhan.

   • Minimizing the Recomputation Time in Soft Error Tolerant Matrix Multiplication Algorithms

     1st HiPEAC Workshop on Design for Reliability (DFR?09)

     Costas Argyrides, Carlos Arthur Lisboa, Luigi Carro & Dhiraj Pradhan.

   • Automatic Generation of C from Event-B

     Workshop on Integration of Model-based Formal Methods and Tools

     Steve Wright.

   • Single Error Correctable Bit Parallel Multipliers Over GF(2^m)

     IET Computers & Digital Techniques

     Jimson Mathew, A. M. Jabir, H. Rahaman & Dhiraj Pradhan.

   • Single Ended 6T SRAM with Isolated Read-Port for Low-Power Embedded Systems

     12th IEEE International Conference on Design Automation and Test in Europe (DATE), 2009

     J Singh, D K Pradhan, S Hollis, S P Mohanty & J Mathew.

   • C-testable S-box Implementation for Secure Advanced Encryption Standard

     IEEE International Online Test Syposium (IOLTS 2009)

     H Rahaman, Jimson Mathew & Dhiraj Pradhan.

   • Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems

     IEEE International Conference on VLSI Design

     Jawar Singh, Jimson Mathew, S. P. Mohanty & Dhiraj Pradhan.

   • Formal Model for the Reduction of the Dynamic Energy Consumption in Multi-Layer Memory Subsystems

     IEICE Transactions

     H. Zhu, I. Lucian, F. Balasa & Dhiraj Pradhan.

   • AN O(m2)-DEPTH QUANTUM ALGORITHM FOR THE ELLIPTIC CURVE DISCRETE LOGARITHM PROBLEM OVER GF(2^m)

     Journal of Quantum Information & Computation

     D. Maslov, Jimson Mathew, D. Cheung & Dhiraj Pradhan.

   • Error Tolerant Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m)

     International Journal of Electronic Science and Technology

     A.K Singh, A Bera, H. Rahaman, Jimson Mathew & Dhiraj Pradhan.

   • A Technique to Identify and Substitute Faulty Nodes in Wireless Sensor Networks

     The Third International Conference on Sensor Technologies and Applications, Greece

     Anas Abu Taleb, C. Taskin & Dhiraj Pradhan.

   • A Fast Error Correction Technique for Matrix Multiplication Algorithms

     International Online Testing Symposium (IOLTS 09)

     Costas Argyrides, Carlos Lisboa, Luigi Carro & Dhiraj Pradhan.

   • Multiple Event Upsets Aware FPGAs Using Protected Schemes

     Dagstuhl Seminar Proceedings on Fault-Tolerant Distributed Algorithms on VLSI Chips

     Costas Argyrides & Dhiraj Pradhan.

   • Single Element Correction in Sorting Algorithms with Minimum Delay Overhead

     At the 10th IEEE Latin-American Test Workshop (LATW09)

     Costas Argyrides, Carlos Lisboa, Luigi Carro & Dhiraj Pradhan.

   • Transition Fault Detection in Bit Parallel Multipliers over GF(2^m)

     Transactions on Circuits and Systems

     H. Rahaman, Jimson Mathew, A. K Singh & Dhiraj Pradhan.

   • Secure Testable S-box Architecture for Cryptographic Hardware Implementation

     The Computer Journal

     H. Rahaman, Jimson Mathew & Dhiraj Pradhan.

   • Test Generation in Systolic Architecture for Multiplication over GF(2^m)

     IEEE Transactions on VLSI Systems

     H. Rahaman, Jimson Mathew & Dhiraj Pradhan.

   • Increasing Memory Yield in Future Technologies through Innovative Design

     IEEE International Symposium on Quality Electronic Design. (ISQED 09)

     Costas Argyrides, Carlos Lisboa, Ahmad Al Yamani, Luigi Carro & Dhiraj Pradhan.

   • MIDAS Machine Specification

     Steve Wright.

   • A novel fault diagnosis technique in wireless sensor networks

     International Journal on Advances in Networks and Services

     Abu Taleb, A, Matthew, J, Pradhan, DK & Kocak, T.

   • A toolset for the analysis and optimization of motion estimation algorithms and processors

     International Conference on Field Programmable Logic and Applications, 2009 (FPL 2009), Prague

     Spiteri, T, Vafiadis, G & Nunez-Yanez, JL.

   • Run-time resource management in fault-tolerant network on reconfigurable chips

     International Conference on Field Programmable Logic and Applications, 2009 (FPL 2009), Prague

     Hosseinabady, M & Nunez-Yanez, JL.

   • A biophysically accurate floating point somatic neuroprocessor

     International Conference on Field Programmable Logic and Applications, 2009 (FPL 2009), Prague

     Zhang, Y, Nunez-Yanez, JL, McGeehan, JP, Regan, EM & Kelly, S.

   • A technique to identify and substitute faulty nodes in wireless sensor networks

     Third International Conference on Sensor Technologies and Applications, 2009 (SENSORCOMM '09), Athens

     Taleb, AA, Pradhan, DK & Kocak, T.

   • Backward adaptive pixel-based fast predictive motion estimation

     IEEE Signal Processing Letters

     Chen, X, Canagarajah, CN & Nunez-Yanez, JL.

5. 2008

   • Adaptive routing strategies for fault-tolerant on-chip networks in dynamically reconfigurable systems

     IET Computers & Digital Techniques

     Nunez-Yanez, JL, Edwards, D & Coppola, AM.

   • C-Testable Bit Parallel Multipliers Over GF(2m)

     ACM Transactions on Design Automation of Electronic Systems (TODAES)

     H. Rahaman, Jimson Mathew, Dhiraj Pradhan & A. M. Jabir.

   • Merging Built-in Current Sensor with H-Tree Architecture for SRAM Reliability Improvement

     IEEE Latin American Test Workshop (LATW 08)

     Costas Argyrides, Fabian Vargas & Dhiraj Pradhan.

   • Single Error Correcting Finite Field Multipliers over GF(2m)

     21st Conference on VLSI Design VLSI 08

     Jimson Mathew, Costas Argyrides, A. Jabir & Dhiraj Pradhan.

   • Embedding Current Monitoring in H-Tree RAM Architecture for Multiple SEU Tolerance and Reliability Improvement

     IEEE International On-Line Testing Symposium

     Costas Argyrides, Fabian Vargas & Dhiraj Pradhan.

   • Area Reliability trade-off in Improved Reed Muller Coding

     SAMOS VIII

     Costas Argyrides, Stephania Loizidou Himona & Dhiraj Pradhan.

   • Yield Improvement and Power Aware Low Cost Memory Chips

     Proceedings of Computing Frontiers 2008

     Costas Argyrides, Stephania Loizidou Himona & Dhiraj Pradhan.

   • Midas Design Document

     Stephen Wright.

   • Algorithm Level Fault Tolerance: a Technique to Cope with Long Duration Transient Faults in Matrix Multiplication Algorithms

     IEEE VLSI Test Symposium (VTS) 2008

     Carlo Lisboa, Costas Argyrides, Dhiraj Pradhan & Luigi Carro.

   • Fault-Tolerant Computing

     Joshi, Dhiraj Pradhan & Jack Stifler.

   • Multiple SEU Tolerance in LUTs of FPGAs Using Protected Schemes

     9th European Conference on Radiation Effects on Components and Systems ? RADECS 2008

     Costas Argyrides, H. Zarandi & Dhiraj Pradhan.

   • Realization of Low Power High-Speed Channel Filters with Stringent Adjacent Channel Attenuation

     IEICE Trasactions

     Jimson Mathew, R. Mahesh, A.P Vinod & L. Edmund.

   • On the Synthesis of Bit-Parallel Galois Field Multipliers with On-line SEC and DED

     Jimson Mathew, A Jabir, H. Rahaman, Costas Argyrides & Dhiraj Pradhan.

   • A Single Ended 6T SRAM Cell Design for Ultra-Low-Voltage Applications

     IEICE Electronics Express

     Jawar Singh, Dhiraj Pradhan, Simon Hollis & Saraju Mohanty.

   • Using EventB to Create a Virtual Machine Instruction Set Architecture

     Abstract State Machines, B and Z

     Steve Wright.

   • Failure Analysis for Ultra Low Power Nano-CMOS SRAM Under Process Variations

     IEEE International System On Chip Conference (SOCC? 2008)

     Jawar Singh, Jimson Mathew & Dhiraj Pradhan.

   • Derivation of Reduced Test Vectors for Bit Parallel Multipliers over GF(2^m)

     IEEE Transactions on Computers

     H. Rahaman, Jimson Mathew & Dhiraj Pradhan.

   • GfXpress: A Technique for Synthesis and Optimization of GF(2^m )Polynomials

     IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,

     A. M. Jabir, Dhiraj Pradhan & Jimson Mathew.

   • Simultaneous scheduling and binding for low gate leakage nano-complementary metal-oxide-semiconductor data path circuit behavioural synthesis

     IET Computers & Digital Techniques (CDT)

     S. P. Mohanty, E. Kougianos & Dhiraj Pradhan.

   • A Defect Tolerance Scheme for Nanotechnology Circuits

     IEEE Trans. On Circuits and Sytems I

     Al-Yamani, Ramsundar & Dhiraj Pradhan.

   • Fault-tolerant dynamically reconfigurable NoC-based SoC

     International Conference on Application-Specific Systems, Architectures and Processors (ASAP2008), Leuven, Belgium

     Hosseinabady, M & Nunez-Yanez, JL.

   • Statistical lossless compression of space imagery and general data in a reconfigurable architecture

     NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2008), Noordwijk, Netherlands

     Nunez-Yanez, JL, Chen, X, Canagarajah, CN & Vitulli, R.

   • A configurable and programmable motion estimation processor for the H.264 video codec

     International Conference on Field Programmable Logic and Applications (FPL 2008), Heidelberg, Germany

     Nunez-Yanez, JL, Eddie, H & Chouliaras, V.

   • Lossless compression for space imagery in a dynamically reconfigurable architecture

     4th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications (ARC 2008), London, UK

     Chen, X, Canagarajah, CN, Vitulli, R & Nunez-Yanez, JL.

   • Evaluating dynamic partial reconfiguration in the integer pipeline of a FPGA-based opensource processor

     International Conference on Field Programmable Logic and Applications, 2008 (FPL 2008), Heidelberg

     Zaidi, SIH, Nabina, A, Canagarajah, CN & Nunez-Yanez, JL.

   • Power/area analysis of a FPGA-based open-source processor using partial dynamic reconfiguration

     11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, 2008 (DSD '08)

     Zaidi, SIH, Nabina, A, Canagarajah, CN & Nunez-Yanez, JL.

   • A Novel ?? Control Stystem Processor and its VLSI implementation

     IEEE Transactions on Very Large Scale Integration (VLSI) Systems

     Wu, X, Chouliaras, VA, Nunez-Yanez, JL & Goodall, RM.

6. 2007

   • Pulse-based, On-chip Interconnect

     Hollis, SJ.

   • A Technique for Representing Multiple Output Binary Functions with Applications to Verification and Simulation

     IEEE Transactions on Computers

     A. M. Jabir, Dhiraj Pradhan, Raja Thiruchi Loganthan & A. Singh.

   • A Triple-Mode Feed-Forward Sigma-Delta Modulator Design For GSM / WCDMA / WLAN Applications

     20th IEEE International System On Chip Conference (IEEE SOCC 2007), September 2007.

     B. R. Jose, Jimson Mathew, P. Mythili & Dhiraj Pradhan.

   • A Novel Soft Error Tolerant Low Power RAM Architecture

     20th annual symposium on Integrated circuits and system design SBCCI '07

     Costas Argyrides, Carlo Lisboa, Luigi Carro & Dhiraj Pradhan.

   • Highly Reliable Power Aware Memory Design

     EEE International On-Line Testing Symposium 2007 (IOLTS)

     Costas Argyrides & Dhiraj Pradhan.

   • Reliable Network-on-Chip Based on Generalized de Bruijn Graph

     IEEE International High Level Design Validation and Test Workshop (HLDVT) (to appear)

     M. Hosseinabady, M. Reza, Jimson Mathew & Dhiraj Pradhan.

   • Fast Reed Muller Decoding for Multi-Bit Upset Aware Memory Designs

     Proccedings of Latin American Test Workshop (LATW)

     Costas Argyrides, Demetriou S & Dhiraj Pradhan.

   • CLB-based Detection and Correction of Bit-flip faults in SRAM-based FPGAs

     Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS)

     H.R. Zarandi, S.G. Miremadi, Costas Argyrides & Dhiraj Pradhan.

   • CAD-Directed SEU Susceptibility Reduction in FPGA Circuits Designs

     IEEE International Conference on Circuits and Systems, (ISCAS 2007), USA

     H. Zarandi, S. G. Miremadi, Dhiraj Pradhan & Jimson Mathew.

   • Soft Error Mitigation in Switch Modules of SRAM-Based FPGAs

     IEEE International Conference on Circuits and Systems, (ISCAS 2007), USA

     H. Zarandi, S. G. Miremadi, Dhiraj Pradhan & Jimson Mathew.

   • On the Hardware Reduction of z-Datapath of Vectoring CORDIC

     IEEE International Conference on Circuits and Systems, (ISCAS 2007), USA

     R. Stapenhurst, Koushik Maharatna, Jimson Mathew, J. Nunez-Yanez & Dhiraj Pradhan.

   • Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m)

     VLSI Design, 2007

     H. Rahaman, Jimson Mathew & Dhiraj Pradhan.

   • A Graph-Based Unified Technique for Computing and Representing Coefficients over Finite Fields

     IEEE Transactions on Computers

     A.M Jabir & Dhiraj Pradhan.

   • Application of de Bruijn graphs to NoC design

     Design Automation and Test in Europe Workshops, DATE07-WKS

     M. Hosseinabady, Jimson Mathew & Dhiraj Pradhan.

   • Efficient Testable Bit Parallel Multipliers over GF(2^m) with Constant Test Set

     13th IEEE International On-Line Testing Symposium,Greece

     Jimson Mathew, H. Rahaman & Dhiraj Pradhan.

   • ?High Defect Tolerant Low Cost Memory Chips

     20th IEEE International System On Chip Conference (SOCC? 2007)

     Costas Argyrides, Ahmad Al-Yamani & Dhiraj Pradhan.

   • Improved Decoding Algorithm for High Reliable Reed Muller Coding

     20th IEEE International System On Chip Conference (SOCC? 2007)

     Costas Argyrides & Dhiraj Pradhan.

   • Matrix Codes: Multiple Bit Upsets Tolerant Method for SRAM Memories

     22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'07)

     Costas Argyrides, Hamid Zarandi & Dhiraj Pradhan.

   • Fast SEU Detection and LUT Configuration Bits of SRAM-based FPGAs

     Proceedings of 14th IEEE Reconfigurable Architecture Workshop, in associated with IPDPS

     H.R. Zarandi, S.G. Miremadi, Costas Argyrides & Dhiraj Pradhan.

   • Non-square Meshes for Improved Yield in Nanotechnology Circuits

     Proccedings of Latin American Test Workshop

     Costas Argyrides, Ramsundar S, Ahmnad Al-Yamani & Dhiraj Pradhan.

   • Multiple Upsets Tolerance in SRAM Memory

     Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS)

     Costas Argyrides, H.R. Zarandi & Dhiraj Pradhan.

   • Online Detection and Correction of Soft-Errors in LUTs of SRAM-based FPGAs

     Proceedings of European Test Symposium (ETS)

     H.R. Zarandi, S.G. Miremadi, Costas Argyrides & Dhiraj Pradhan.

   • ?Efficient Method to Tolerate Multiple Bit Upsets in SRAM Memory?

     Proceedings of European Test Symposium (ETS)

     Costas Argyrides, H.R. Zarandi & Dhiraj Pradhan.

   • Dynamic voltage scaling in a FPGA-based system-on-chip

     2007 International Conference on Field Programmable Logic and Applications, (FPL 2007), Amsterdam, Netherlands

     Nunez-Yanez, JL, Chouliaras, VA & Gaisler, Jiri.

   • Thread-parallel MPEG-2 and MPEG-4 encoders for shared-memory system-on-chip multiprocessors

     International Journal of Computers and Applications

     Chouliaras, VA, Jacobs, TR, Nunez-Yanez, JL, Manolopoulos, K, Nakos, K & Reisis, D.

   • Towards Automating Simulation-Based Design Verification Using ILP

     Inductive Logic Programming, 16th International Conference, ILP 2006, Santiago de Compostela, Spain, August 24-27, 2006

     Eder, KI, Flach, PA & Hsueh, H-W.

7. 2006

   • A Low Power 128-Pt Implementation of FFT/IFFT for High Performance Wireless Personal Area Networks

     IEEE PRIME Conference

     Jimson Mathew, Koushik Maharatna & Dhiraj Pradhan.

   • Exploration of Power optimal Implementation Technique of 128-Pt FFT/IFFT for WPAN using Pseudo- Parallel Datapath Strcuture

     IEEE International Conference on Communication Systems, Singapore

     Jimson Mathew, Koushik Maharatna & Dhiraj Pradhan.

   • An Efficient Technique for Synthesis and Optimization of Polynomials in GF(2m)

     IEEE International Conference on Computer Aided Design

     A. Jabir, Dhiraj Pradhan & Jimson Mathew.

   • An Asynchronous Interconnect Architecture for Device Security Enhancement

     19th International Conference on VLSI Design

     Simon Hollis & Simon W. Moore.

   • An area-efficient, pulse-based interconnect

     IEEE International Symposium on Circuits and Systems (ISCAS)

     Simon Hollis & S. W. Moore.

   • Easily Testable Implementation for Bit Parallel Multipliers in GF(2m)

     IEEE International High Level Design Validation and Test Workshop(HLDVT)

     H. Rahaman, Jimson Mathew, Dhiraj Pradhan & A.M. Jabir.

   • RasP: An Area-efficient, On-chip Network

     24th International Conference on Computer Design (ICCD)

     Simon Hollis & Simon W. Moore.

   • CSPIC - a Low-power Microcontroller

     David May.

   • A Language and Processor for Unifying System-on-Chip Design

     Douglas Watt & David May.

   • Towards Automating Simulation-Based Design Verification using ILP

     16th International Conference on Inductive Logic Programming

     Kerstin Eder, Peter Flach, Hsiou-Wen Hsueh, Stephen Muggleton, Ramon Otero & Alireza Tamaddoni-Nezhad.

   • Test Directive Generation for Functional Coverage Closure Using Inductive Logic Programming

     IEEE International High Level Design Validation and Test Workshop (HLDVT) 2006

     Hsiou-Wen Hsueh & Kerstin Eder.

   • Performance Analysis of an Error Tolerant Low Power Memory Architecture

     IEEE International Design and Test Workshop

     Costas Argyrides, Jimson Mathew, Ahmad Al-Yamani & Dhiraj Pradhan.

   • Accelerating speech coding standards through SystemC- synthesized SIMD and scalar accelerators

     International Conference on Consumer Electronics (ICCE '06), Las Vegas, USA, 7-11 January

     Koutsomyti, K, Chouliaras, V, Parr, SR, Nunez-Yanez, JL & Datta, S.

   • Hardware assisted rate distortion optimization with embedded CABAC accelerator for the H.264 advanced video codec

     IEEE Transactions on Consumer Electronics

     Nunez-Yanez, JL, Chouliaras, VA, Alfonso, D & Rovati, F.

   • Test Directive Generation for Functional Coverage Closure Using Inductive Logic Programming

     11th Annual IEEE International High Level Design Validation and Test Workshop, Monterey, California, November 2006

     Hsueh, H-W & Eder, KI.

   • Reuse-Based Test Access and Integrated Test Scheduling for Network-on-Chip

     Design, Automation and Test in Europe Conference and Exhibition

     Liu, C, Link, Z & Pradhan, D.

   • Gigabyte per second streaming lossless data compression hardware based on a configurable variable-geometry CAM dictionary

     IEE Proceedings - Computers and Digital Techniques

     Nunez-Yanez, JL & Chouliaras, VA.

8. 2005

   • NiVER: Non-increasing Variable Elimination Resolution for Preprocessing SAT Instances

     Lecture Notes in Computer Science,Springer

     S. Subbarayan & Dhiraj Pradhan.

   • Towards Inducing Stimulus Generation Directives from Functional Coverage Data

     Kerstin Eder & Hsiou-Wen Hsueh.

   • Configurable multiprocessors for high-performance MPEG-4 video coding

     IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design, Tampa, FL, United States

     Chouliaras, VA, Jacobs, TR, Kumaraswamy, Ashwin K & Nunez-Yanez, JL.

   • High-performance arithmetic coding VLSI macro for the H264 video compression standard

     IEEE Transactions on Consumer Electronics

     Nunez-Yanez, JL & Chouliaras, VA.

   • A multi-standard video accelerator based on a vector architecture

     IEEE Transactions on Consumer Electronics

     Chouliaras, VA, Nunez-Yanez, JL, Rovati, F & Alfonso, D.

   • EBIST: a novel test generator with built-in fault detection capability

     IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

     Pradhan, DK & Liu, C.

   • An Efficient Graph Based Representation of Circuits and Calculation of Their Coefficients in Finite Field

     Fourteenth International Workshop on Logic and Synthesis

     Jabir, A & Pradhan, D.

   • Galois Switching Theory: A Uniform Framework for Multi-Level Verification

     Fourteenth International Workshop on Logic and Synthesis

     Pradhan, D, Singh, A, Rajaprabhu, T & Jabir, A.

   • Comparative Study of CA with Phase Shifters and GLFSRs

     International Test Conference 2005

     Chidambaram, S, Kagaris, D & Pradhan, D.

   • A Hamming Distance Based Test Pattern Generator With Improved Fault Coverage

     IEEE International On-Line Testing Symposium

     Pradhan, D & Kagaris, D.

   • A configurable statistical lossless compression core based on variable order modelling and arithmetic coding

     IEEE Transactions on Computers

     Nunez-Yanez, JL & Chouliaras, VA.

9. 2004

   • Development of custom vector accelerator for high-performance speech coding

     Electronics Letters

     Chouliaras, VA, Nunez-Yanez, JL, Koutsomyti, K, Parr, SR, Mulvaney, DJ & Datta, S.

   • Design and implementation of a lossless parallel high-speed data compression system

     IEEE Transactions on Parallel and Distributed Systems

     Milward, M, Nunez-Yanez, JL & Mulvaney, D.

   • NIVER: Non Increasing Variable Elimination Resolution for Preprocessing SAT Instances

     In Selected Revised Papers of International Conference on Theory and Applications of Satisfiability Testing Conference (Springer LNCS)

     Subbarayan, S & Pradhan, D.

   • NiVER: Non-increasing Variable Elimination Resolution for Preprocessing SAT Instances

     Lecture Notes in Computer Science (3542)

     Subbarayan, S & Pradhan, DK.

   • MODD for CF: a representation for fast evaluation of multiple-output functions

     Ninth IEEE International High-Level Design Validation and Test Workshop, 2004.

     Rajaprabhu, TL, Singh, AK, Jabir, AM & Pradhan, D.

   • Test scheduling for network-on-chip with BIST and precedence constraints

     International Test Conference, 2004. Proceedings.

     Chunsheng Liu, Cota, E, Sharif, H & Pradhan, DK.

   • MODD: a new decision diagram and representation for multiple output binary functions

     Design, Automation and Test in Europe Conference and Exhibition, Paris, 16-20 February

     Jabir, AM & Pradhan, DK.

   • Design and implementation of a lossless parallel high-speed data compression system

     IEEE Transactions on Parallel and Distributed Systems

     Nunez-Yanez, JL, Milward, JL & Mulvaney, D.

10. 2003

    • Structural and Algebraic Coding Theory Based Approach to SAT Solvers

      Dhiraj K Pradhan.

    • Reconfigurable computing and active networks

      International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA'03) Las Vegas, NV, USA

      Bartzoudis, NG, Fragkiadakis, AG, Parish, DJ, Nunez-Yanez, JL & Sandford, MJ.

    • Scalar coprocessors for accelerating the G723.1 and G729A speech coders

      IEEE Transactions on Consumer Electronics

      Chouliaras, VA & Nunez-Yanez, JL.

    • Run-length coding extensions for high performance hardware data compression

      IEE Proceedings - Computers and Digital Techniques

      Nunez-Yanez, JL & Jones, S.

    • Gbit/s lossless data compression hardware

      IEEE Transactions on Very Large Scale Integration (VLSI) Systems

      Nunez-Yanez, JL & Jones, S.

    • EBIST: a novel test generator with built-in fault detection capability

      Design, Automation and Test in Europe Conference and Exhibition, 2003

      Pradhan, D, Chunsheng Liu & Chakraborty, K.

    • Wormhole routing in de Bruijn networks and hyper-de Bruijn networks

      International Symposium on Circuits and Systems, 2003.

      Ganesan, E & Pradhan, D.

    • Logic transformation and coding theory-based frameworks for Boolean satisfiability

      Eighth IEEE International High-Level Design Validation and Test Workshop, 2003.

      Pradhan, D.

    • Mathematical framework for representing discrete functions as word-level polynomials

      Eighth IEEE International High-Level Design Validation and Test Workshop, 2003

      Pradhan, D, Askar, S & Ciesielski, M.

    • Mathematical framework for representing discrete functions as word-level polynomials

      Eighth IEEE International High-Level Design Validation and Test Workshop, San Francisco, 12-14 November

      Pradhan, DK, Askar, S & Ciesielski, M.

    • A BIST pattern generator design for near-perfect fault coverage

      ieeetc

      Chatterjee, M & Pradhan, D.

11. 2002

    • Caches with Compositional Performance

      Embedded Processor Design Challenges

      Henk Muller, Ed F Deprette, Dan Page, Jurgen Teich, James Irwin, Stamasis Vassiliadis & David May.

    • Predictable Instruction Caching for Media Processors

      13th International Conference on Application-specific Systems, Architectures and Processors (ASAP)

      Irwin, J, May, D, Muller, HL & Page, D.

    • Achieving maximum performance: a method for the verification of interlocked pipeline control logic

      39th Design Automation Conference, New Orleans, 10-14 June

      Eder, KI & Barrett, G.

12. 2001

    • Picochip Instruction Set Proposal

      David May.

    • Logic insertion to speed-up logic verification: a recent development

      Seventh International On-Line Testing Workshop, 2001. Proceedings.

      Pradhan, D.

    • Random Register Renaming to Foil DPA

      Lecture Notes in Computer Science (2162)

      May, MD, Muller, HL & Smart, NP.

    • Non-deterministic Processors

      Lecture Notes in Computer Science (2119)

      May, MD, Muller, HL & Smart, NP.

    • The 'Uniform Heterogeneous Multi-threaded' Processor Architecture

      Concurrent Systems Engineering series

      Towner, DW & May, MD.

    • Copying, Moving and Borrowing semantics

      Communicating Process Architectures -- 2001

      May, D & Muller, HL.

13. 2000

    • Buffer assignment algorithms on data driven ASICs

      IEEE Transactions on Computers,

      Chatterjee, M. , Banerjee, S. & Dhiraj Pradhan.

    • VERILAT: verification using logic augmentation and transformations

      IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,

      D. Paul, M. Chatterjee & Dhiraj Pradhan.

    • Effective Caching for Multithreaded Processors

      Communicating Process Architectures 2000

      David May, P. H. Welch, James Irwin, A. W. P. Bakkers, Henk L Muller & Dan Page.

    • Synchronisation in a Multithreaded Processor

      Communicating Process Architectures 2000

      Shondip Sen, P. H. Welch, Henk Muller, A. W. P. Bakkers & David May.

    • Cache Memory

      David May & Henk Muller.

    • Hardware Migratable Channels

      Euro-Par 2000 Parallel Processing

      David May, Henk Muller & Shondip Sen.

    • Hardware Migratable Channels

      David May, Henk Muller & Shondip Sen.