Power switches are increasingly becoming dominant leakage power reduction technique for sub-100nm CMOS tech- nology. Hence, fast and effective DFT for test and diagnosis of power switches is much needed with an aim to facilitating faster identiﬁcation of potential faults and their locations. In this paper, we present a novel coarse-grain DFT solution enabling divide and conquer based test and diagnosis scheduling of power switches. The proposed solution beneﬁts from exponential time savings compared to previously reported approaches. The test and diagnosis time savings are further substantiated through effective discharge circuit design that eliminates the possibility of false test by reducing the charge and discharge times signif- icantly. We validated the effectiveness of our solution through SPICE simulations on a number of ISCAS benchmark circuits synthesized using a 90nm gate library. It takes 2⌈log2 m⌉ + 3 clock cycles in the worst case for an m-bit segment for test and diagnosis of power switches.