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A Novel Si-Tunnel FET SRAM Design for Ultra Low-Power 0.3V VDD Application

Jawar Singh, K. Ramakrishnan , S. Mookerjea, S. Datta, V. Narayanan, Dhiraj Pradhan, A Novel Si-Tunnel FET SRAM Design for Ultra Low-Power 0.3V VDD Application. To appear in the proceedings of 15th Asia South Pacific Design Automation Conference (ASPDAC), January, Taipei, Taiwan, 2010.. January 2010. No electronic version available.

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