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Instruction Stream Mutation for Non-Deterministic Processors

J. Irwin, D. Page, N. P. Smart, Instruction Stream Mutation for Non-Deterministic Processors. 13th International Conference on Application-specific Systems, Architectures and Processors (ASAP). M. Shulte, S. Bhattacharyya, N. Burgess, R. Schreiber, (eds.). ISBN 0-7695-1712-9, pp. 286–295. July 2002. PDF, 103 Kbytes.

Abstract

Differential power analysis (DPA) has become a real-world threat to the security of cryptographic hardware devices such as smart-cards. By using cheap and readily available equipment, attacks can easily compromise algorithms running on these devices in a non-invasive manner. Adding non-determinism to the execution of cryptographic algorithms has been proposed as a defence against these attacks. One way of achieving this non-determinism is to introduce random additional operations to the algorithm which produce noise in the power profile of the device. We describe the addition of a specialised processor pipeline stage which increases the level of potential non-determinism and hence guards against the revelation of secret information.

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