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Interrupt and control packets for a microcomputer

David May, Andrew Jones, Interrupt and control packets for a microcomputer. Patent. EP959412. November 1999. No electronic version available. External information


An integrated circuit chip (11) has an address and data path (15) interconnecting at least one CPU (12) with a different module (15), the CPU and module each having event logic (8,44) to generate event request packets of two types, each having a destination address, one type being a control packet to which a destination device must respond on receipt and the other type including a priority indicator such that the destination device can selectively respond depending on the priority detected.

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