Publications by Dhiraj Pradhan

This is a list of all publications (co-)authored by Dhiraj Pradhan that are contained in the publications database of the Department of Computer Science, University of Bristol. To perform an alternative search of the publications database, please go to the publications database home page.

2013

Mike Huang, Jimson Mathew, Rishad Shafik, Subhasis Bhattacharjee, Dhiraj Pradhan, A Fast and Effective DFT for Test and Diagnosis of Power Switches in SOCs. Design, Automation, and Test in Europe (DATE) Conference. February 2013. No electronic version available.
Jimson Mathew, S.P.Mohanty, Dhiraj Pradhan, Attack Tolerant Cryptographic Hardware Design by Combining Error Correction and Uniform Switching Activity. Elsevier Journal of Electrical and Computer Engineering, . January 2013. No electronic version available.

2012

F. Balasa, Dhiraj Pradhan, Integrated Software Tools for the Memory Management of Low-Energy Embedded Signal Processing System. 5th International Congress on Image and Signal Processing (CISP 2012) . November 2012. PDF, 323 Kbytes.
Galadanci, J, Shafik, R.A, Jimson Mathew, Dhiraj Pradhan, A Closed-loop Control Strategy for Glucose Control in Artificial Pancreas Systems. In: IEEE Computer Society Intl. Symposium on Electronic Systems Design. October 2012. No electronic version available.
I. Sourdis, C. Strydis, C. Bouganis, B.Falsafi, Dhiraj Pradhan, Rishad Shafik, The DeSyRe project: on-Demand System Reliability (invited paper). 15th EUROMICRO Conference on Digital System Design (DSD),. September 2012. No electronic version available.
Jimson Mathew, Patra P., Dhiraj Pradhan, Kuttyamma, A.J, Eco-friendly Computing and Communication Systems. . ISBN 978-3-642-32111-5. August 2012. No electronic version available.
Narayanan, V.K, Shafik, R.A, Jimson Mathew, Dhiraj Pradhan, Fault Tolerant High Performance Galois Field Arithmetic Processor. Lecture Notes in Computer Science, . August 2012. No electronic version available.
H Rahaman, Jimson Mathew, A. M. Jabir, Dhiraj Pradhan, VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF(2m)Using Dual Bases . Lecture note in Computer Science (LNCS) , Springer. ISSN 0302-9743, pp. 258–269. July 2012. No electronic version available.
S P Mohanty, J Singh, E. Kougianos, Dhiraj Pradhan, Statistical DOE-ILP based power-performance-process (P3) optimization of nano-CMOS SRAM. Integration, the VLSI Journal, 45( ), pp. 33–45. June 2012. PDF, 4827 Kbytes.
R. A. Shafik, B. M. Al-Hashimi, Jimson Mathew, Dhiraj Pradhan, S. P. Mohanty, RAEF: A Power Normalized System-Level Reliability Analysis and Estimation Framework. 1th IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 189–194. June 2012. No electronic version available.
P. Yeolekar, R. A. Shafik, Jimson Mathew, Dhiraj Pradhan, S. P. Mohanty, “STEP: A Unified Design Methodology for Secure Test and IP Core Protection. 21st ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), , 2012 , pp. 333–338. May 2012. No electronic version available.
J.Singh, MohantyS.P, Dhiraj Pradhan, Robust SRAM Designs and Analysis. Springer. ISBN 978-1-4614-0817-8 . January 2012. No electronic version available.
L. Sun,, Jimson Mathew, Dhiraj Pradhan, S. P. Mohanty, “Enhanced Statistical Blockade Approaches for Fast Robustness Estimation and Compensation of Nano-CMOS Circuits. Journal of Low Power Electronics (JOLPE), 8(3), pp. 261–269. January 2012. No electronic version available.

2011

F. Balasa, Dhiraj Pradhan, Energy-Aware Memory Management for Embedded Multimedia Systems: A Computer-Aided Design Approach. Chapman & Hall / CRC Press. ISBN 1439814007/ 978-1439814000. December 2011. No electronic version available.
Hosseinabady, M, Jimson Mathew, Mohanty, Dhiraj Pradhan, Single-Event Transient Analysis in High Speed Circuits. International Symposium on Electronic System Design (ISED), 2011 , pp. 112–117. December 2011. No electronic version available.
Luo Sun, Jimson Mathew, Dhiraj Pradhan, Saraju Mohanty, Statistical Blockade Method for Fast Robustness Estimation and Compensation of Nano-CMOS Arithmetic Circuits. IInternational Symposium on Electronic System Design (ISED), , pp. 194–1999. December 2011. No electronic version available.
S. Banerjee, Jimson Mathew, S.P. Mohanty, Dhiraj Pradhan, M. Ciesielski, A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization. Journal of Low Power Electronics, 7(4), pp. 471–481. December 2011. No electronic version available.
M. Hosseinabady, R. Kakoee, Jimson Mathew, Dhiraj Pradhan, Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn Graph. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 99, pp. 1469 –1480. September 2011. PDF, 2054 Kbytes.
V. Misra, Jimson Mathew, Dhiraj Pradhan, Fault-tolerant De-Bruijn Graph Based Multipurpose Architecture and Routing Protocol for WSN. International Journal of Sensor Networks (IJSNet), . May 2011. No electronic version available.
Jimson Mathew, K. Maharatna, Dhiraj Pradhan, Pseudo-parallel Datapath Structure for Power Optimal Implementation of 128-pt FFT/IFFT for Wireless Personal Area Networks. Circuits, Systems, and Signal Processing, . ISBN ISSN: 0278-081X. April 2011. No electronic version available.
Mahesh P., Jimson Mathew, A.M. Jabir, Dhiraj Pradhan, S. P. Mohanty, BCH Code Based Multiple Bit Error Correction in Finite Field Multiplier Circuits. Proceedings of the 12th IEEE International Symposium on Quality Electronic Design (ISQED),. ISSN 29696771. March 2011. No electronic version available.
S. Banerjee, Jimson Mathew, Dhiraj Pradhan, A Routing-Aware ILS Design Technique. at IEEE Transactions on Very Large Scale Integration Systems , . ISSN 1063-8210. March 2011. No electronic version available.
S. Banerjee, Jimson Mathew, Dhiraj Pradhan, S.P. Mohanty, Variation-Aware TED- Based Approach for Nano-CMOS RTL Leakage Optimization. IEEE 24th International Conference on VLSI Design. ISSN 1063-8210. January 2011. No electronic version available.

2010

Jimson Mathew, P. Mahesh, A.M. Jabir, Dhiraj Pradhan, Multiple bits Error Detection and Correction in GF Arithmetic Circuits. International Symposium on Electronic System Design (ISED). December 2010. No electronic version available.
S. Mohanty, Dhiraj Pradhan, DOE-ILP Based Simultaneous Power and Read Stability Optimization in Nano-CMOS SRAM. Journal of Low Power Electronics, 6(3). October 2010. No electronic version available.
Anas Abu Taleb, Jimson Mathew, Dhiraj Pradhan, Efficient Fault Tolerant De Bruijn Based Design Approach for Sensor Networks. 4^th International Conference on Sensor Technologies and Applications, 2010. SENSORCOMM , Italy. July 2010. No electronic version available.
H. Rahaman, Jimson Mathew, A. Jabir, Dhiraj Pradhan, Simplified Bit Parallel Systolic Multipliers for Special Class of GF(2m) with Testability. IET Computers and Digital Techniques, . July 2010. No electronic version available.
Anas Abu Taleb, Jimson Mathew, Dhiraj Pradhan, Fault Diagnosis in Multi Layered De Bruijn Based Architectures for Sensor Networks. 6^th IEEE Int Workshop on Sensor Networks and Systems for Pervasive computing((PerSeNs 2010). June 2010. No electronic version available.
S.P. Mohanty, Dhiraj Pradhan, ULS: A Dual-Vth/High-K Nano-CMOS Universal Level Shifter for System-Level Power Management. ACM Journal of Emerging Technologies in Computing (JETC), 6(2), pp. 8:1-8–26. June 2010. No electronic version available.
Luo Sun, Jimson Mathew, Dhiraj Pradhan, S. P. Mohanty, Algorithms for Rare Event Analysis in Nano-CMOS Circuits Using Statistical Blockade. Proceedings of the International SoC Design Conference (ISOCC). May 2010. No electronic version available.
G. Thakral, S. P. Mohanty, D. Ghai, Dhiraj Pradhan, A DOE-ILP Assisted Conjugate-Gradient Approach for Power and Stability Optimization in High-κ/Metal-Gate SRAM. ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), pp. 323–328. May 2010. No electronic version available.
G. Thakral, S. P. Mohanty, Dhiraj Pradhan, P3 (Power-Performance-Process) Optimization of Nano-CMOS SRAM using Statistical DOE-ILP. 11th IEEE International Symposium on Quality Electronic Design (ISQED). May 2010. No electronic version available.
Anas Abu Taleb, Jimson Mathew, Dhiraj Pradhan, Clustered De Bruijn Multi Layered Architectures for Sensor Networks. Lecture notes in Computer Science. April 2010. No electronic version available.
Jimson Mathew, Dhiraj Pradhan, On the Design of Different Concurrent EDC Schemes for S-box and GF(P)",. Proceedings of the 11th IEEE International Symposium on Quality Electronic Design (ISQED). March 2010. No electronic version available.
Anas Abu Taleb, Jimson Mathew, Dhiraj Pradhan, A Novel Fault Diagnosis Technique in Wireless Sensor Networks. The International Journal On Advances in Networks and Services, . March 2010. No electronic version available.
Andrew Ricketts, Jawar Singh, Vijaykrishnan Narayanan, Dhiraj Pradhan, Investigating the Impact of NBTI on Different Power Saving Cache Strategies. To appear in the proceedings of IEEE International Conference, DATE, 2010, Germany. March 2010. PDF, 274 Kbytes.
Jimson Mathew, A Jabir, A.K Singh, H.Rahaman, Dhiraj Pradhan, A Galois Field Based Logic Synthesis Approach with Testability. IET Computers & Digital Techniques, . March 2010. No electronic version available.
Dhiraj Pradhan, . Patent. . February 2010. No electronic version available.
G. Thakral, S. P. Mohanty, D. Ghai, Dhiraj Pradhan, A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM. IEEE International Conference on VLSI Design (VLSID 10). February 2010. No electronic version available.
G. Thakral, S. P. Mohanty, Dhiraj Pradhan, A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM. IEEE International Conference on VLSI Design (VLSID). January 2010. No electronic version available.
Jawar Singh, K. Ramakrishnan , S. Mookerjea, S. Datta, V. Narayanan, Dhiraj Pradhan, A Novel Si-Tunnel FET SRAM Design for Ultra Low-Power 0.3V VDD Application. To appear in the proceedings of 15th Asia South Pacific Design Automation Conference (ASPDAC), January, Taipei, Taiwan, 2010.. January 2010. No electronic version available.

2009

Jimson Mathew, A. M. Jabir, H. Rahaman, Dhiraj Pradhan, Single Error Correctable Bit Parallel Multipliers Over GF(2^m). IET Computers & Digital Techniques, . December 2009. No electronic version available.
H. Rahaman, Jimson Mathew, Dhiraj Pradhan, Test Generation in Systolic Architecture for Multiplication over GF(2^m). IEEE Transactions on VLSI Systems, . November 2009. No electronic version available.
Costas Argyrides, Pedro Reviriego, Juan A. Maestro, Dhiraj Pradhan, A novel error correction technique for adjacent errors. 10th European Conference on Radiation Effects on Components and Systems – RADECS 2009. September 2009. No electronic version available.
H Rahaman, Jimson Mathew, Dhiraj Pradhan, C-testable S-box Implementation for Secure Advanced Encryption Standard. IEEE International Online Test Syposium (IOLTS 2009). July 2009. No electronic version available.
H. Zhu, I. Lucian, F. Balasa, Dhiraj Pradhan, Formal Model for the Reduction of the Dynamic Energy Consumption in Multi-Layer Memory Subsystems. IEICE Transactions , 53(12). July 2009. PDF, 446 Kbytes.
D. Maslov, Jimson Mathew, D. Cheung, Dhiraj Pradhan, AN O(m2)-DEPTH QUANTUM ALGORITHM FOR THE ELLIPTIC CURVE DISCRETE LOGARITHM PROBLEM OVER GF(2^m). Journal of Quantum Information & Computation, 9(7), pp. 0610–0627. July 2009. No electronic version available.
A.K Singh, A Bera, H. Rahaman, Jimson Mathew, Dhiraj Pradhan, Error Tolerant Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m),. International Journal of Electronic Science and Technology, . July 2009. No electronic version available.
Costas Argyrides, Giorgos Dimosthenous, Carlos Lisboa, Luigi Carro, Dhiraj Pradhan, Reliability Aware Yield Improvement Technique for Nanotechnology Based Circuits. 22nd annual symposium on Integrated circuits and system design SBCCI ‘09. July 2009. No electronic version available.
Costas Argyrides, Carlos Lisboa, Luigi Carro, Dhiraj Pradhan, A Fast Error Correction Technique for Matrix Multiplication Algorithms. International Online Testing Symposium (IOLTS 09). July 2009. No electronic version available.
Jimson Mathew, A Jabir, H. Rahaman, Costas Argyrides, Dhiraj Pradhan, On the Synthesis of Bit-Parallel Galois Field Multipliers with On-line SEC and DED. , . July 2009. No electronic version available.
Anas Abu Taleb, C. Taskin, Dhiraj Pradhan, A Technique to Identify and Substitute Faulty Nodes in Wireless Sensor Networks.. The Third International Conference on Sensor Technologies and Applications, Greece. June 2009. No electronic version available.
H. Rahaman, Jimson Mathew, A. K Singh, Dhiraj Pradhan, Transition Fault Detection in Bit Parallel Multipliers over GF(2^m). Transactions on Circuits and Systems, . May 2009. No electronic version available.
H. Rahaman, Jimson Mathew, Dhiraj Pradhan, Secure Testable S-box Architecture for Cryptographic Hardware Implementation. The Computer Journal, . April 2009. No electronic version available.
J Singh, D K Pradhan, S Hollis, S P Mohanty, J Mathew, Single Ended 6T SRAM with Isolated Read-Port for Low-Power Embedded Systems. 12th IEEE International Conference on Design Automation and Test in Europe (DATE), 2009. April 2009. No electronic version available.
Costas Argyrides, Dhiraj Pradhan, Multiple Event Upsets Aware FPGAs Using Protected Schemes. Dagstuhl Seminar Proceedings on Fault-Tolerant Distributed Algorithms on VLSI Chips. March 2009. No electronic version available.
Costas Argyrides, Carlos Lisboa, Luigi Carro, Dhiraj Pradhan, Single Element Correction in Sorting Algorithms with Minimum Delay Overhead. At the 10th IEEE Latin-American Test Workshop (LATW09). March 2009. No electronic version available.
Costas Argyrides, Carlos Lisboa, Ahmad Al Yamani, Luigi Carro, Dhiraj Pradhan, Increasing Memory Yield in Future Technologies through Innovative Design. IEEE International Symposium on Quality Electronic Design. (ISQED 09) . March 2009. No electronic version available.
Jawar Singh, Jimson Mathew, S. P. Mohanty, Dhiraj Pradhan, Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems. IEEE International Conference on VLSI Design, pp. 307–312. February 2009. No electronic version available.
Costas Argyrides, Carlos Arthur Lisboa, Luigi Carro, Dhiraj Pradhan, Minimizing the Recomputation Time in Soft Error Tolerant Matrix Multiplication Algorithms. 1st HiPEAC Workshop on Design for Reliability (DFR’09). January 2009. No electronic version available.

2008

Al-Yamani, Ramsundar, Dhiraj Pradhan, A Defect Tolerance Scheme for Nanotechnology Circuits. IEEE Trans. On Circuits and Sytems I, . December 2008. No electronic version available.
Costas Argyrides, H. Zarandi, Dhiraj Pradhan, Multiple SEU Tolerance in LUTs of FPGAs Using Protected Schemes. 9th European Conference on Radiation Effects on Components and Systems – RADECS 2008. September 2008. No electronic version available.
Jawar Singh, Dhiraj Pradhan, Simon Hollis, Saraju Mohanty, A Single Ended 6T SRAM Cell Design for Ultra-Low-Voltage Applications . IEICE Electronics Express, 5(18). ISSN 1349-2543, pp. 750–755. September 2008. PDF, 1109 Kbytes. External information
Jawar Singh, Jimson Mathew, Dhiraj Pradhan, Failure Analysis for Ultra Low Power Nano-CMOS SRAM Under Process Variations. IEEE International System On Chip Conference (SOCC’ 2008). . September 2008. No electronic version available.
M. Hosseinabady, R. Kakoee, Jimson Mathew, Dhiraj Pradhan, De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs. Proceedings of the conference on Design, automation and test in Europe (DATE 2008), pp. 1370–1273. August 2008. PDF, 142 Kbytes.
H. Rahaman, Jimson Mathew, Dhiraj Pradhan, Derivation of Reduced Test Vectors for Bit Parallel Multipliers over GF(2^m). IEEE Transactions on Computers , . August 2008. No electronic version available.
Costas Argyrides, Fabian Vargas, Dhiraj Pradhan, Embedding Current Monitoring in H-Tree RAM Architecture for Multiple SEU Tolerance and Reliability Improvement. IEEE International On-Line Testing Symposium. July 2008. No electronic version available.
Joshi, Dhiraj Pradhan, Jack Stifler, Fault-Tolerant Computing. John Wiley & Sons. June 2008. No electronic version available. External information
Costas Argyrides, Stephania Loizidou Himona, Dhiraj Pradhan, Yield Improvement and Power Aware Low Cost Memory Chips. Proceedings of Computing Frontiers 2008. May 2008. No electronic version available.
A. M. Jabir, Dhiraj Pradhan, Jimson Mathew, GfXpress: A Technique for Synthesis and Optimization of GF(2^m )Polynomials. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, , 27(4). ISSN 0278-0070, pp. 698–711. April 2008. PDF, 657 Kbytes.
Costas Argyrides, Stephania Loizidou Himona, Dhiraj Pradhan, Area Reliability trade-off in Improved Reed Muller Coding. SAMOS VIII . April 2008. No electronic version available.
Carlo Lisboa, Costas Argyrides, Dhiraj Pradhan, Luigi Carro, Algorithm Level Fault Tolerance: a Technique to Cope with Long Duration Transient Faults in Matrix Multiplication Algorithms. IEEE VLSI Test Symposium (VTS) 2008, . April 2008. No electronic version available.
S. P. Mohanty, E. Kougianos, Dhiraj Pradhan, Simultaneous scheduling and binding for low gate leakage nano-complementary metal-oxide-semiconductor data path circuit behavioural synthesis. IET Computers & Digital Techniques (CDT), 2(2), pp. 118–131. March 2008. PDF, 488 Kbytes.
Costas Argyrides, Fabian Vargas, Dhiraj Pradhan, Merging Built-in Current Sensor with H-Tree Architecture for SRAM Reliability Improvement. IEEE Latin American Test Workshop (LATW 08). February 2008. No electronic version available.
Jimson Mathew, Costas Argyrides, A. Jabir, Dhiraj Pradhan, Single Error Correcting Finite Field Multipliers over GF(2m). 21st Conference on VLSI Design VLSI 08. January 2008. No electronic version available.
H. Rahaman, Jimson Mathew, Dhiraj Pradhan, A. M. Jabir, C-Testable Bit Parallel Multipliers Over GF(2m). ACM Transactions on Design Automation of Electronic Systems (TODAES), . January 2008. No electronic version available.

2007

M. Hosseinabady, M. Reza, Jimson Mathew, Dhiraj Pradhan, Reliable Network-on-Chip Based on Generalized de Bruijn Graph. IEEE International High Level Design Validation and Test Workshop (HLDVT) (to appear). November 2007. No electronic version available.
B. R. Jose, Jimson Mathew, P. Mythili, Dhiraj Pradhan, A Triple-Mode Feed-Forward Sigma-Delta Modulator Design For GSM / WCDMA / WLAN Applications. 20th IEEE International System On Chip Conference (IEEE SOCC 2007), September 2007. . September 2007. No electronic version available.
Costas Argyrides, Ahmad Al-Yamani, Dhiraj Pradhan, “High Defect Tolerant Low Cost Memory Chips. 20th IEEE International System On Chip Conference (SOCC’ 2007). September 2007. No electronic version available.
Costas Argyrides, Dhiraj Pradhan, Improved Decoding Algorithm for High Reliable Reed Muller Coding. 20th IEEE International System On Chip Conference (SOCC’ 2007). September 2007. No electronic version available.
Costas Argyrides, Hamid Zarandi, Dhiraj Pradhan, Matrix Codes: Multiple Bit Upsets Tolerant Method for SRAM Memories. 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'07). September 2007. No electronic version available.
Costas Argyrides, Carlo Lisboa, Luigi Carro , Dhiraj Pradhan, A Novel Soft Error Tolerant Low Power RAM Architecture. 20th annual symposium on Integrated circuits and system design SBCCI '07. September 2007. No electronic version available.
A. M. Jabir, Dhiraj Pradhan, Raja Thiruchi Loganthan, A. Singh, A Technique for Representing Multiple Output Binary Functions with Applications to Verification and Simulation . IEEE Transactions on Computers, 56(8). ISBN ISSN: 0018-9340, pp. 1133–1145. August 2007. PDF, 3746 Kbytes.
A.M Jabir, Dhiraj Pradhan, A Graph-Based Unified Technique for Computing and Representing Coefficients over Finite Fields . IEEE Transactions on Computers, 56(8). ISBN ISSN: 0018-9340, pp. 1119–1132. August 2007. PDF, 4546 Kbytes.
Costas Argyrides, Dhiraj Pradhan, Highly Reliable Power Aware Memory Design. EEE International On-Line Testing Symposium 2007 (IOLTS). July 2007. No electronic version available.
Jimson Mathew, H. Rahaman, Dhiraj Pradhan, Efficient Testable Bit Parallel Multipliers over GF(2^m) with Constant Test Set. 13th IEEE International On-Line Testing Symposium,Greece. June 2007. No electronic version available.
H.R. Zarandi, S.G. Miremadi, Costas Argyrides, Dhiraj Pradhan, CLB-based Detection and Correction of Bit-flip faults in SRAM-based FPGAs ,. Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS). May 2007. No electronic version available.
Costas Argyrides, H.R. Zarandi, Dhiraj Pradhan, Multiple Upsets Tolerance in SRAM Memory. Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS). May 2007. No electronic version available.
H.R. Zarandi, S.G. Miremadi, Costas Argyrides, Dhiraj Pradhan, Online Detection and Correction of Soft-Errors in LUTs of SRAM-based FPGAs. Proceedings of European Test Symposium (ETS). May 2007. No electronic version available.
Costas Argyrides, H.R. Zarandi, Dhiraj Pradhan, “Efficient Method to Tolerate Multiple Bit Upsets in SRAM Memory”. Proceedings of European Test Symposium (ETS). May 2007. No electronic version available.
H. Zarandi, S. G. Miremadi, Dhiraj Pradhan, Jimson Mathew, CAD-Directed SEU Susceptibility Reduction in FPGA Circuits Designs. IEEE International Conference on Circuits and Systems, (ISCAS 2007), USA. May 2007. No electronic version available.
H. Zarandi, S. G. Miremadi, Dhiraj Pradhan, Jimson Mathew, Soft Error Mitigation in Switch Modules of SRAM-Based FPGAs. IEEE International Conference on Circuits and Systems, (ISCAS 2007), USA. May 2007. No electronic version available.
R. Stapenhurst, Koushik Maharatna, Jimson Mathew, J. Nunez-Yanez, Dhiraj Pradhan, On the Hardware Reduction of z-Datapath of Vectoring CORDIC. IEEE International Conference on Circuits and Systems, (ISCAS 2007), USA. May 2007. No electronic version available.
M. Hosseinabady, Jimson Mathew, Dhiraj Pradhan, Application of de Bruijn graphs to NoC design. Design Automation and Test in Europe Workshops, DATE07-WKS , pp. 111–116. March 2007. No electronic version available.
H.R. Zarandi, S.G. Miremadi, Costas Argyrides, Dhiraj Pradhan, Fast SEU Detection and LUT Configuration Bits of SRAM-based FPGAs,. Proceedings of 14th IEEE Reconfigurable Architecture Workshop, in associated with IPDPS. March 2007. No electronic version available.
Costas Argyrides, Demetriou S, Dhiraj Pradhan, Fast Reed Muller Decoding for Multi-Bit Upset Aware Memory Designs. Proccedings of Latin American Test Workshop (LATW). March 2007. No electronic version available.
Costas Argyrides, Ramsundar S, Ahmnad Al-Yamani, Dhiraj Pradhan, Non-square Meshes for Improved Yield in Nanotechnology Circuits. Proccedings of Latin American Test Workshop. March 2007. No electronic version available.
H. Rahaman, Jimson Mathew, Dhiraj Pradhan, Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m). Chapter in VLSI Design, 2007, pp. 479–484. January 2007. No electronic version available.

2006

A. Jabir, Dhiraj Pradhan, Jimson Mathew, An Efficient Technique for Synthesis and Optimization of Polynomials in GF(2m). IEEE International Conference on Computer Aided Design. ISBN 1-59593-389-1, pp. 151–157. November 2006. No electronic version available.
H. Rahaman, Jimson Mathew, Dhiraj Pradhan, A.M. Jabir, Easily Testable Implementation for Bit Parallel Multipliers in GF(2m). IEEE International High Level Design Validation and Test Workshop(HLDVT). November 2006. No electronic version available.
Costas Argyrides, Jimson Mathew, Ahmad Al-Yamani, Dhiraj Pradhan, Performance Analysis of an Error Tolerant Low Power Memory Architecture. IEEE International Design and Test Workshop. November 2006. PDF, 333 Kbytes.
Jimson Mathew, Koushik Maharatna, Dhiraj Pradhan, A Low Power 128-Pt Implementation of FFT/IFFT for High Performance Wireless Personal Area Networks. IEEE PRIME Conference, pp. 377–380. June 2006. No electronic version available.
C. Liu, Z. Link, Dhiraj Pradhan, Reuse-Based Test Access and Integrated Test Scheduling for Network-on-Chip. Design, Automation and Test in Europe Conference and Exhibition. March 2006. PDF, 777 Kbytes.
Jimson Mathew, Koushik Maharatna, Dhiraj Pradhan, Exploration of Power optimal Implementation Technique of 128-Pt FFT/IFFT for WPAN using Pseudo- Parallel Datapath Strcuture. IEEE International Conference on Communication Systems, Singapore. February 2006. No electronic version available.

2005

S.Chidambaram, D. Kagaris, Dhiraj Pradhan, Comparative Study of CA with Phase Shifters and GLFSRs. International Test Conference 2005. November 2005. No electronic version available.
S. Subbarayan, Dhiraj Pradhan, NiVER: Non-increasing Variable Elimination Resolution for Preprocessing SAT Instances. Lecture Notes in Computer Science,Springer, 3542/2005. ISBN 978-3-540-27829-0, pp. 276–291. August 2005. No electronic version available.
Dhiraj Pradhan, Chunsheng Liu, EBIST: A Novel Test Generator with Built-in fault Detection Capability. ieeetcad, 24(8). August 2005. PDF, 354 Kbytes.
A. Jabir , Dhiraj Pradhan, An Efficient Graph Based Representation of Circuits and Calculation of Their Coefficients in Finite Field . Fourteenth International Workshop on Logic and Synthesis . June 2005. No electronic version available.
Dhiraj Pradhan, A. Singh, T. Rajaprabhu, A. Jabir , Galois Switching Theory: A Uniform Framework for Multi-Level Verification . Fourteenth International Workshop on Logic and Synthesis . June 2005. No electronic version available.
Dhiraj Pradhan, D. Kagaris , A Hamming Distance Based Test Pattern Generator With Improved Fault Coverage. IEEE International On-Line Testing Symposium. June 2005. PDF, 130 Kbytes.

2004

T.L. Rajaprabhu, A.K. Singh, A.M. Jabir, Dhiraj Pradhan, MODD for CF: a representation for fast evaluation of multiple-output functions. Ninth IEEE International High-Level Design Validation and Test Workshop, 2004. . ISSN 1552-6674 , pp. 61–66. November 2004. PDF, 2043 Kbytes.
Chunsheng Liu Cota, Sharif, H, Dhiraj Pradhan, Test scheduling for network-on-chip with BIST and precedence constraints. International Test Conference, 2004. Proceedings. , pp. 1369 –1378. November 2004. PDF, 962 Kbytes.
S. Subbarayan, Dhiraj Pradhan, NIVER: Non Increasing Variable Elimination Resolution for Preprocessing SAT Instances. In Selected Revised Papers of International Conference on Theory and Applications of Satisfiability Testing Conference (Springer LNCS), , pp. 276–291. May 2004. PDF, 171 Kbytes.
S. Subbarayan, Dhiraj Pradhan, NiVER: Non Increasing Variable Elimination Resolution. Proceedings of The Seventh International Conference on Theory and Applications of Satisfiability Testing (SAT '04), pp. 351–356. May 2004. PDF, 179 Kbytes.
Bhattacharjee, S, Dhiraj Pradhan, LPRAM: a novel low-power high-performance RAM design with testability and scalability. ieeetcad, 23(5). ISSN 0278-0070 , pp. 637–651. May 2004. PDF, 492 Kbytes.
A.M. Jabir, Dhiraj Pradhan, MODD: a new decision diagram and representation for multiple output binary functions. Design, Automation and Test in Europe Conference and Exhibition, 2004. ISSN 1530-1591 , pp. 1388 –1389. February 2004. PDF, 221 Kbytes.

2003

Dhiraj Pradhan, Logic transformation and coding theory-based frameworks for Boolean satisfiability. Eighth IEEE International High-Level Design Validation and Test Workshop, 2003. . ISBN 0-7803-8236-6, pp. 57–62. December 2003. PDF, 342 Kbytes.
Dhiraj Pradhan, Askar, S. , Ciesielski, M. , Mathematical framework for representing discrete functions as word-level polynomials. Eighth IEEE International High-Level Design Validation and Test Workshop, 2003. ISBN INSPEC Accession Number:790724, pp. 135–139. December 2003. PDF, 205 Kbytes.
Dhiraj Pradhan, Askar, S, Ciesielski, M, Mathematical framework for representing discrete functions as word-level polynomials. Eighth IEEE International High-Level Design Validation and Test Workshop, 2003. ISSN 1552-6674, pp. 135–139. December 2003. PDF, 205 Kbytes.
Mitrajit Chatterjee , Dhiraj Pradhan, A BIST pattern generator design for near-perfect fault coverage. ieeetc, 52(12). ISSN 0018-9340 , pp. 1543 –1558 . December 2003. PDF, 580 Kbytes.
Dhiraj Pradhan, Chunsheng Liu , Chakraborty, K, EBIST: a novel test generator with built-in fault detection capability. Design, Automation and Test in Europe Conference and Exhibition, 2003 . ISSN 1530-1591 , pp. 224–229. May 2003. PDF, 296 Kbytes.
Ganesan, E., Dhiraj Pradhan, Wormhole routing in de Bruijn networks and hyper-de Bruijn networks. International Symposium on Circuits and Systems, 2003. . May 2003. PDF, 283 Kbytes.
Dhiraj K Pradhan, Structural and Algebraic Coding Theory Based Approach to SAT Solvers. CSTR-03-003, Department of Computer Science, University of Bristol. March 2003. No electronic version available. External information

2001

Dhiraj Pradhan, Logic insertion to speed-up logic verification: a recent development. Seventh International On-Line Testing Workshop, 2001. Proceedings. , pp. 61–64. July 2001. PDF, 254 Kbytes.

2000

D. Paul, M. Chatterjee, Dhiraj Pradhan, VERILAT: verification using logic augmentation and transformations. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, , 19(9). ISSN 0278-0070 , pp. 1041 – 1051 . September 2000. PDF, 294 Kbytes.
Chatterjee, M. , Banerjee, S. , Dhiraj Pradhan, Buffer assignment algorithms on data driven ASICs. IEEE Transactions on Computers, , 49(1). ISBN 0018-9340 , pp. 16–32. January 2000. PDF, 518 Kbytes.

1996

Bowen, N.S, Dhiraj Pradhan, The effect of program behavior on fault observability. , IEEE Transactions on Computers, 45(8). ISSN 0018-9340 , pp. 868–880. August 1996. PDF, 1422 Kbytes.
Chakradhar, S.T., Banerjee, S., Roy, R.K., Dhiraj Pradhan, Synthesis of initializable asynchronous circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, , 4(2). ISSN 1063-8210 , pp. 254–263. June 1996. PDF, 1182 Kbytes.
Gupta, S.K. , Dhiraj Pradhan, Utilization of on-line (concurrent) checkers during built-in self-test and vice versa. ieeetc: IEEE Transactions on Computers , 63 (73). ISSN 0018-9340 , pp. 45–1. January 1996. PDF, 1217 Kbytes.
Kunz, W. , Dhiraj Pradhan, Reddy, S.M. , A novel framework for logic verification in a synthesis environment. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, , 15(1). ISBN 0278-0070 , pp. 20–32. January 1996. PDF, 1473 Kbytes.