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Design Automation and Verification Group


Members of the Design Automation and Verification (DAV) Group share a common interest in the specification, design, analyisis and verification of both software and hardware systems. Current research interests include: The DAV Group has been formed in March 2000 to promote collaboration between researchers who share the same interests. It has close links with the Languages and Architecture Group.

The group aims to expand its research activities into system-level functional verification techniques both formal and simulation based. We have long established links with a number of local and international companies such as Infineon, STMicroelectronics, Broadcom, Cadence and IBM, who provide some of their designs or tools for collaborative research projects.

We plan to expand the verification research, for timing optimization and performance/power verification. Low-power designs provide the major challenges for the chip design in the future. What we are exploring here is power estimation technique for both combinational and sequential logic, as well as power optimization techniques. Additionally being explored here are new approaches to SAT-solvers - a fundamental problem in computer science. This has many applications to CAD as well as to verification.