Introduction to Swallow
We are working on the production of a 480 processor embedded system, based on the XMOS XS1 architecture. The system will be used to explore how large numbers of lightweight (500MHz x 8 threads x 64kB store/core + a fast inter-core interconnect) can be effectively used. The platform is designed to allow energy monitoring of both the cores and the communication, with the aim of producing a system that can illustrate the energy use of parallel, communicating algorithms.
Our research objectives are:
- Investigate programming models for large-scale parallelism.
- Investigate the energy consumption in many-core systems, in particular the balance between computation and communication.
- Provide a platform for understanding the difficulties in composing many cores at the architectural level.
- Answer the question of "How much memory is needed per processing core", for a range of contemporary applications.
- Investigate what happens when a very high ratio of communication ability to storage is provided, and the impact on algorithms.
- Further development of highly parallel algorithms.
The work will be performed in three stages:
- The creation of a 112 processor system, based on the XMOS L2 dual-core chip.
- Addition of DRAM storage and fast, ethernet-based I/O.
- Expansion to 480 cores.
Current progress can be monitored using the links in the side-bar at the top of this page.
Research Team
Academic staff:
 Simon Hollis |
 David May |
Research Students:
 Jamie Hanlon |
 Steve Kerrison |
 James Pallister |