A Practical Introduction to Computer Architecture
SlidesSome related material is available, e.g., lecture slides.
- Page 48 (Axel Eirola). Figure 2.5 has gate (g) labeled as NAND, but of course it should be NOR.
- Page 71 (Axel Eirola). There are some references to table 2.12a and figure2.19a, which should be table 2.12b and figure 2.19b.
- Page 82 (Axel Eirola). In Figure 2.29 the value of signal b changes 30ns after the change in en. The text on page 80 states that the delay of the AND gate is 20ns so the pulse in signal b should therefore be drawn 10ns to the eariler (i.e., to the left).
- Page 179 (Dan Page).
The table for communication between P and Q has the last two lines
the wrong way around; it should read
P Q c_1=1 -> <- c_2=1 x -> c_1=0 -> <- c_2=0such that Q knows when P has sent the value x and should hence try to read it.
- Page 243 (Dan Page).
Figure 7.8 (of a logarithmic shifter) has
\log_2(n)in the last box which is clearly mad: the overall number of boxes (i.e., steps) is logarithmic in
nbut clearly the last shift distance should be by
- Page 292 and 315 (Axel Eirola). The chapter reference for pipelines is wrong: it says 6, but should be 9.
- Page 299 (Axel Eirola). Second paragraph labels the parity bit for x'_4, x'_5 and x'_6 as p_4, while in the subsequent text it is referred to as p_3. Also, in the second to last paragraph x'=1001100 should be x'=0011001 since if p_0=0, p_1=0, p_3=1 and x_0=1, x_1=0, x_2=0, x_3=1, with x'=(p_0, p_1, x_0, p_3, x_1, x_2, x_3), then this equals (0, 0, 1, 1, 0, 0, 1).
- Page 314 (Dan Page). The text reads "there are four sets each of two lines" but this does not match the numbers; it should read "there are two sets each of four lines".
- Page 330 (Dan Page).
Question 36 states that the arrays declarations are changed to
a, b, c;but for the answer to make sense, this should be
a, b, c;
- Page 577 to 578 (Luke Fitzgerald).
The answer to question 9.a is a bit dubious. In short, the table
(and hence expressions) say that if you see the sequence ACA, for
example, then the state machine resets. This is wrong, it should
go back into the state where one A has been read. So the table
S_1 S_0 I_1 I_0 S'_1 S'_0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 0 0 0 0 1 1 1 0 0 1 0 0 0 0 1 1 0 0 1 0 0 1 0 1 0 0 0 1 0 1 1 1 1 1 1 0 0 0 1 1 1 0 1 0 0 1 1 1 0 0 0 1 1 1 1 0 0which makes the expressions that generate
S'_0(before any simplification) into
S'_0 = ( \NOT S_1 \AND \NOT S_0 \AND \NOT I_1 \AND \NOT I_0 ) \OR ( \NOT S_1 \AND S_0 \AND \NOT I_1 \AND \NOT I_0 ) \OR ( S_1 \AND \NOT S_0 \AND \NOT I_1 \AND \NOT I_0 ) \OR ( S_1 \AND S_0 \AND \NOT I_1 \AND \NOT I_0 ) \OR ( S_1 \AND \NOT S_0 \AND I_1 \AND I_0 ) S'_1 = ( \NOT S_1 \AND S_0 \AND \NOT I_1 \AND I_0 ) \OR ( S_1 \AND \NOT S_0 \AND I_1 \AND I_0 )
- Page 345 (Axel Eirola). The text says there are three shift operations in Figure 9.6, there there are four shown.
- Page 581 (Dan Page).
At the end of the answer to question 11.c, there are plus
operators instead of OR operators; the equations should be
N_0 = ( t_5 \AND B_0 ) \OR ( t_5 \AND t_0 ) \OR ( t_3 \AND B_0 \AND t_0 ) N_1 = ( t_4 \AND B_0 ) \OR ( t_4 \AND t_0 ) \OR ( t_5 \AND B_0 ) \OR ( t_5 \AND t_0 )