Current Research Interests
Many-core Implementations and InterconnectNetworks-On-Chip (NoCs) provide the communications fabric for next-generation many-core architectures. NoCs provides a modular, structured network with predictable latency and bandwidth characteristics, offering advantages over developing application-specific networks. My current key areas of interest relating to NoCs include:
- Routing algorithms
- Energy efficiency
- Network topology
- Interconnect fabric
- Software NoC simulation and artificial traffic generation
Dynamic Reconfigurable TopologiesMost contemporary NoC architectures use a fixed arrangement of links and routers, typically in a Mesh, Torus or Hypercube topology. The choice of topology is fundamentally more important than a choice of router design, since the topology determines the shortest paths through the network and its related energy and latency costs. Topologies that map well to an underlying application give efficient systems, and increasingly we see research that look to bridge the performance gap between inflexible application specific topologies and general purpose NoCs. I am currently investigating NoC architectures capable of runtime topology-reconfiguration. This has led to interesting problems in routing (formal methods), synchronisation (asynchronous circuit design) and inter-node communications (complexity and geometry). The methods for dynamic topology reconfiguration are inspired by goal-oriented feedback-loop emergent networks.
Routing AlgorithmsRouting algorithms decide the path taken through a network for each discrete element of traffic. Although routing algorithms have been studied in-depth for many types of network (LAN, WAN, telephone etc) there is still much work to be completed in the context of NoCs.
Currently I am designing routing relations and selection functions for dynamic mesh topologies. These algorithms ensure that a network remains deadlock-free and all source-destination pairs are routable, while the topology is reconfigured at runtime.