Chris Jackson

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Publications List

Journal papers

Chris Jackson and Simon J. Hollis, A Deadlock-free Routing Algorithm for Dynamically Reconfigurable Networks-on-Chip, Published ub Elsevier Micpro : Special issue on Networks-on-Chip (NoCs), 2010. Elsevier version

We address routing in Networks-On-Chip (NoC) architectures that use irregular mesh topologies with Long-Range Links (LRL). These topologies create diffi- cult conditions for routing algorithms, as standard algorithms assume a static, regular link structure and exploit the uniformity of regular meshes to avoid deadlock and maintain routability. We present a novel routing algorithm that can cope with these irregular topologies and adapt to runtime LRL insertion and topology reconfiguration. Our approach to accommodate dynamic topology reconfiguration is to use a new technique that decomposes routing relations into two stages: the calculation of output ports on the current minimal path and the application of routing restrictions designed to prevent deadlock. In addition, we present a selection function that uses local topology data to adaptively select optimal paths. The routing algorithm is shown to be deadlock-free, after which an analysis of all possible routing decisions in the region of an LRL is carried out. We show that the routing algorithm minimises the cost of sub-optimally placed LRL and display the hop savings available. When applied to LRLs of less than seven hops, the overall traffic hop count and associated routing energy cost is reduced. In a simulated 8 × 8 network the total input buffer usage across the network was reduced by 6.5%.

Chris Jackson and Simon J. Hollis, Simon J. Hollis and Chris Jackson. Implementation and evaluation of skip-links: A dynamically reconfiguring topology for energy-efficient nocs., International Journal for Embedded and Real-time Computer Systems (IJERTCS), July-September 2011. PDF version

We introduce the Skip-link architecture that dynamically reconfigures Networkon- Chip (NoC) topologies, in order to reduce the overall switching activity in many-core systems. The proposed architecture allows the creation of long-range Skip-links at runtime to reduce the logical distance between frequently communicating nodes. This offers a number of advantages over existing methods of creating optimised topologies already present in the literature such as the Reconfigurable NoC (ReNoC) architecture and static Long-Range Link (LRL) insertion. Our architecture monitors traffic behaviour and optimises the mesh topology without prior analysis of communications behaviour, and is thus applicable to all applications. Our technique does not utilise a master node, and each router acts independently. The architecture is thus scalable to future many-core networks. We evaluate the performance using a cycle-accurate simulator with synthetic traffic patterns and compare the results to a mesh architecture, demonstrating logical hop count reductions of 12–17%. Coupled with this, we observe up to a doubling in critical load and the potential for 10% energy reductions on a 16 ×: 16 node network.

Fully refereed conference papers

Simon J. Hollis and Chris Jackson, "When does Network-on-Chip Bypassing Make Sense?", 22nd IEEE SoCC Conference, September 2009. PDF version

Networks-on-Chip (NoCs) are becoming widespread in contemporary multi-core and many-core designs. Amongst their appeals are regularity of layout and flexibility of topology. However, the energy consumed by routing nodes is now vastly more than that of an ALU operation in one of the processing cores they service. We present an evaluation of bypassing, a technique where selected traffic can avoid the full routing functionality of selected nodes in a NoC. When implemented correctly, bypassing can dramatically reduce the overall energy consumption of data flowing through the network. We address the questions of when bypassing should be deployed at a given node, how much energy will be saved by doing so, and present some equations to quantify and answer these questions. We show that if 74 to 80% of data, depending on router implementation, is destined for a node further away than that employing bypassing, then bypassing is energy-effective. Using these figures, we define guidelines for the use of bypassing for a wide variety of NoC designs.

Chris Jackson and Simon J. Hollis , "Skip-Links: A Dynamically Reconfiguring Topology for Energy Efficient NoCs", The International Symposium for System On Chip, September 2010. PDF version

We introduce the Skip-link architecture that dynamically reconfigures Network-on-Chip (NoC) topologies, in order to reduce the overall switching activity in many-core systems. The proposed architecture allows the creation of long-range Skip- links at runtime to reduce the logical distance between frequently communicating nodes. This offers a number of advantages over existing methods of creating optimised topologies already present in the literature such as the Reconfigurable NoC (ReNoC) architecture and static Long-Range Link (LRL) insertion. Our architecture monitors traffic behaviour and optimises the mesh topology without prior analysis of communications behaviour, and is thus applicable to all applications. Our technique does not utilise a master node, and each router acts independently. The architecture is thus scalable to future many-core networks. We evaluate the performance using a cycle-accurate simulation with synthetic traffic patterns and compare the results to a mesh architecture, demonstrating hop count and energy reductions of around 10%.

Invited papers

Simon J. Hollis and Chris Jackson, "Skip the analysis: Self-optimising Network-on-chips" (invited paper). Electronic System Design, International Symposium on, 2010.PDF version

In this paper, we investigate how the need for static analysis of data flowing through Networks-on-Chip in many-core and SoC systems may be eliminated, yet still allow network optimisations to improve runtime behaviour. Our approach is to replace a priori static analysis with run-time optimisations, taking place in the network itself. To do this, we introduce our self-optimising NoC topology: Skip-links, which inserts long-range links into a standard mesh. We evaluate the performance of Skip-links at run-time against the optimal configuration, as determined by static analysis, for both the transpose and tornado traffic patterns. We show that the local decision-making algorithm employed by Skip-links comes close to optimum, carrying 70% of theoretical maximum traffic flows for tornado traffic, and reducing average hop counts by 18% for transpose traffic.

Workshop papers

Chris Jackson and Simon Hollis, "Initialisation and Synchronisation for a Dynamic Topology Network-On-Chip Architecture", UK Async Forum, September 2009. PDF version

Networks-on-Chip (NoCs) provide a Globally Asynchronous Locally Synchronous communication (GALS) fabric for VLSI. We propose a Network-on-Chip architecture that supports dynamic topology changes. These changes take the form of "bypass paths" that allow routers to be traversed by flits without being buffered or switched. Each individual bypass uses an extra layer of topology switches to directly connect a router's input link to its output link in the opposite direction. When the bypass paths are placed suitably an overall reduction in network router activity is achieved, reducing overall energy expenditure and latency. The architecture is supported by an adaptive deadlock-free routing algorithm that ensures routability. We present two solutions to mitigate potential local synchronisation problems when performing topology alterations: the first allows almost immediate changes and uses an arbiter to ensure flit ordering is maintained; the other introduces a delay but requires no extra logic. In addition, the algorithm that places bypass paths in the network is described.