2nd Year Tutorial "Making DES work on an FPGA - Verilog revisited"

In this tutorial we will revisit Assignment 2 of the "Introduction to Computer Archtecture" (COMS12200) lecture which you had last year. We will use the Verilog implementation of DES (Data Encryption Standard) from that assignment, synthesize it and load it onto one of our Spartan-3 development boards

The target of this tutorial is to explore

• FPGAs and the Spartan as a sample architecture,
• the design space of hardware implementations and trade-offs between efficiency, cost and power consumption and to
• deepen the understanding of the chip development process.

Additional Information:

You should read the assignment of last year's COMS 12200 before the tutorial starts. You do not have to do the assignment, we will work with model solutions. When reading the assignment, focus on the design of DES. (More on DES in the list of additional reading materials.)

Additional Information:

FPGAs (Field Programmable Gate Arrays) are chips that feature an array of configurable logic blocks that are connected to a configurable network of wires. Unlike ASICs, where a circuit is hardwired in silicon, a circuit is loaded into an ASIC by configuring the interconnect network and the logic cells. This makes FPGAs far more versatile than ASICs but comes at the cost of a comparatively reduced speed and stricter limits on the circuit size. However, for many computing intensive applications FPGAs with custom made circuits outperform ASIC CPUs in terms of throughput.

For example, an ASIC cryptography coprocessor implementing DES will provide the highest throughput but has very high development costs and is only affordable in mass production when millions of units are produced. Furthermore, once an ASIC is produced, it can not be changed anymore and has to be replaced with a different ASIC. An FPGA configured to run the same coprocessor circuit (i.e. the same verilog code) will achieve lower throughput and has a higher per unit cost than the ASIC but the initial costs are much lower and the FPGA can be reconfigured after deployment to fix bugs or to support additional functionality. This makes FPGAs very attractive for small and medium volume applications as well as ASIC prototyping. An ASIC CPU in comparison can execute any program and therefor is the most versatile but has a significantly reduced throughput as its architecture is not optimized for the specific application. For example, it may lack registers or parallelism.

The permutations in DES are a good example for this: From the assignment you know that a bit permutation requires just some wiring in hardware and is therefor very efficient. On an ASIC, the permutation is fixed at production and can not be changed afterwards. On an FPGA the wiring is configured and can be changed by reconfiguration. On common CPU architectures the permutation is quite inefficient and has to be implemented using many XORs and shifts which reduces the throughput drastically despite the CPU being produced as an ASIC.

Additional Reading:

• General info: Wikipedia on FPGAs
• General info: Wikipedia on DES
• More sciency info: Sections 8.5.2 and 8.6 (pages 404 - 422) of J.M. Rabaey, A. Chandrakasan, B. Nikolic: "Digital Integrated Circuits - A Design Perspective", Prentice Hall (Section and page numbers refer to the 2nd edition).
• Deep info (don't be scared, this far more than we'll need!): Spartan-3 User Guide
• Deep info (don't be scared, this far more than we'll need!): Spartan Board Documentaion