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Bristol EACO Workshop 6

Special focus of this workshop is on global engagement with the aim to identify new research partners to join forces in advancing the state of the art in energy-aware computing. The programme contains a series of presentations on current research activities in at the University of Bristol and presentations from international guest speakers.

This workshop is being held on Tues 26th and Weds 27th March 2013. For up to date event details, please see the Eventbrite listing for this workshop.

A co-located SIG on energy efficiency is also being held prior to the Tuesday EACO session.

Agenda

  1. Tues 26th March:
  2. 11:30 Registration
  3. 12:00 Welcome and Introduction - David May, University of Bristol
  4. 12:10 Introduction to Energy Aware COmputing at Bristol - Jose Nunez-Yanez and Simon Hollis, University of Bristol
  5. 12:30 Energy proportional computing with Adaptive Voltage and Logic Scaling (AVLS) - Jose Nunez-Yanez, University of Bristol
  6. 12:50 Lunch including Networking
  7. 13:50 Towards On-demand System Reliability - Rishad Shafik, University of Bristol
  8. 14:10 Compiling for Energy-efficient code - Simon Hollis, University of Bristol
  9. 14:30 Discussion followed by short coffee break
  10. 15:10 EACOF: The Energy-Aware COmputing Framework - Lowering the barrier-to-entry for Energy-Aware Programming - Glen Andersson, University of Bristol
  11. 15:20 EACOP: The Energy-Aware COmputing Platform - Simon Hollis, University of Bristol
  12. 15:30 Energy modelling for multi-threaded embedded software - Steve Kerrison, University of Bristol
  13. 15:40 Whole Systems ENgergy TRAnsparency - ENTRA - Kyriakos Georgiou, University of Bristol
  14. 16:00 The CiaoPP Resource Usage Analysis and Verification Framework - Pedro Lopez-Garcia, Researcher, IMDEA Software Institute, Madrid, Spain
  15. ~16:20 Open for additional contributions
  16. 16:30 Discussion and Conclusion from Day 1
  17. 17:00 Drinks Reception and Networking
  18. 18:00 END of formal part Day 1
  19. 20:00 Workshop dinner (tbc)
  20. Weds 27th March:
  21. 8:30 Registration
  22. 8:50 Welcome to Day 2 - Kerstin Eder, University of Bristol
  23. 9:00 Towards zero-power computing - Luca Gammaitoni, Physics Department of the Universita di Perugia, Italy
  24. 10:00 Discussion followed by a short Coffee Break
  25. 10:30 Energy Characterization of Embedded Processors for Software Energy Reduction - Tohru Ishihara, Kyoto University, Japan
  26. 11:30 Open for additional contributions
  27. 12:00 What next? Opportunities for International Collaboration
  28. 13:00 Lunch including Networking
  29. 14:00 END of formal part
  30. 14:15 Room remains available for informal discussions and brainstorming
  31. 17:00 CLOSE, Room will be locked

Abstracts

Energy Characterization of Embedded Processors for Software Energy Reduction
Tohru Ishihara, Kyoto University

The presentation addresses our recent research activities and results on characterizing and reducing the energy consumption in embedded systems. Firstly, a technique for characterizing the energy consumption of embedded processors during an application execution is presented. The technique trains a per-processor linear approximation model for fitting it to the energy consumption of the processor obtained by post-layout simulation. Secondly, based on the energy model mentioned above, the presentation shows techniques for reducing the energy consumption by optimally mapping program code, stack frames and data items to the scratch-pad memory (SPM) of the processor memory space.

Compiling for Energy-efficient code
Simon Hollis, University of Bristol

We know that machine learning can deliver improvements in the run-time of executed code. Can the same methodology give us insights into similar ways to improve energy efficiency. In this talk we discuss results of this to date, and a heads up on a new research effort into machine- learning driven compilation for energy efficiency.

Promoting energy consumption awareness as a first class factor during the software development lifecycle
Kyriakos Georgiou, University of Bristol

This project proposes an energy-aware system development approach covering hardware, software and the run-time environment. The central goal is to make energy usage transparent through the system layers, thus enabling optimizations both during code development and at run- time.

To achieve that we are developing models of energy usage covering all system layers down to the underlying hardware and then analysis techniques which will infer the information gathered from those models about energy consumption, precision and performance for the higher system layers. This will lead to the development of energy specific optimization techniques both at design and run- time enabling software engineers to get advantage of the energy transparency.

The CiaoPP Resource Usage Analysis and Verification Framework
Pedro Lopez-Garcia, Researcher, IMDEA Software Institute

We present a general resource usage analysis framework which isparametric with respect to resources and type of approximation (lower-and upper-bounds). The user can define the parameters of the analysis for a particular resource by means of assertions that associate basic cost functions with elementary operations of programs, thus expressinghow they affect the usage of a particular resource. A global static analysis can then infer bounds on the resource usage of all the procedures in the program, providing such usage bounds as functions of input data sizes. Examples of resources that can be analyzed by instantiating the framework include execution steps, execution time, energy consumption, as well as other user-defined resources, like the number of bits sent or received by an application over a socket, number of calls to a procedure, or number of accesses to a database. Based on the general analysis, we also present a framework for (static) verification of general resource usage program properties. The framework extends the criteria of correctness as the conformance of a program to a specification expressing upper and/or lower bounds on resource usages (given as functions on input data sizes). A novel aspect of the framework is that the outcome of the static checking of assertions can express intervals for the input data sizes such that a given specification can be proved for some intervals but disproved for others.

Towards On-demand System Reliability
Rishad A Shafik, University of Bristol

Fault-tolerant design and testing with of future life-critical systems, such as implantable devices, is highly challenging due to conflicting design trade-offs between performance, power and area overheads. To address this challenge, EU-funded DeSyRe project employs a novel hierarchical hardware/software co-design approach dividing the design and testing tasks in various logical and physical layers. The logical layers define the hardware and software interfaces to achieve system adaptability at low system overheads. On the other hand, the physical partition horizontally divides the system into fault-prone and fault-free parts for efficient system management.

The University of Bristol team leads important tasks related to software implemented fault tolerance and online testing. The software implemented fault tolerance task aims to achieve co-ordination between the logical layers, while providing with software based detection and tolerance of mainly transient faults, particularly suitable for commercial off-the-shelf (COTS) components used in this project. Alongside transient faults, permanent fault syndromes are also generated in the component wrappers using the information related to frequency and nature of the detected faults. When such syndrome is generated, online testing routine is conveniently scheduled to effectively detect the faults.

Toward zero-power computing
Luca Gammaitoni, University of Perugia

Fundamental limits toward zero-power computing are briefly discussed together with the scientific perspective to bring together software and hardware energy-aware strategies for the future ICT.

Energy proportional computing with Adaptive Voltage and Logic Scaling
Jose Nunez-Yanez, University of Bristol

In energy proportional computing the work to be done and the time available to do it defines the amount of energy that should be used. In this talk we investigate how this can be achieved and its benefits if chip capacitance, voltage and frequency are variable. We use commercially available reconfigurable chips to create a variation-aware closed-loop system able to change at run-time these parameters and measure the variation in dynamic/static power, energy and performance. The results show that slower and parallel configurations are the most energy efficient and that up 85% energy improvement is possible with these configurations in current hardware.

EACOP: The Energy-Aware COmputing Platform
Simon Hollis, University of Bristol

Energy-aware computing is a challenge that requires investigating the entire "system stack" from application software and algorithms, via programming languages, compiler tool chains, operating systems, processor instruction sets and micro architectures, down to the hardware.

In EACOP, we aim to bridge the gap between process abstraction and hardware reality by producing:
a) An operating system, customised to capture and pass energy consumption data to running processes, with the aim of modifying their behaviour to maximise energy efficiency.
b) Tests of "Swallow" a real many-core hardware platform, augmented with energy measurement infrastructure, that provides a test platform for executing many hundreds of processes concurrently whilst measuring the impact of process placement and scheduling on energy use.

Energy modelling for multi-threaded embedded software
Steve Kerrison, University of Bristol

Software activity must be correlated with hardware energy consumption in order to establish metrics by which software developers can measure the energy efficiency of the software that they write. Embedded software developers have a particular need for this, often working within resource-constrained systems. This presentation discusses research into the instruction-level energy modelling of a multi-threaded embedded processor - the XMOS XS1-L, demonstrates the key components in software that can influence the energy behaviour of the processor, and shows a model that can be used for generating energy metrics for software at simulation time.

Co-located Energy Efficient Computing SIG Workshop

The following pre-EACO-workshop has been organised for Tues 26th March. More information can be found via __connect. The agenda for the event is as follows:

  1. 9:00 Registration and Coffee
  2. 9:30 Introduction and Welcome (Ian Osborne, ICTKTN)
  3. 9:35 Ian Phillips, ARM: Energy Efficient Computing; Through a 21c Looking Glass
  4. 10:15 John Easton, IBM: When worlds collide: energy efficiency and real world IT
  5. 10:45 Break
  6. 11:00 John Bancroft, STFC: STFC Energy Efficient Computing, a Hartree Centre Perspective
  7. 11:30 marie-Christine Sawley, Intel: Preparing for the Exascale: Energy efficiency from the Application to the HPC center
  8. 12:00 EACO workshop begins as originally scheduled