Publications on Design Verification

2012

Hardware and Software: Verification and Testing - 7th International Haifa Verification Conference, HVC 2011. Kerstin Eder, Joao Lourenco, Onn Shehory, (eds.). Lecture Notes in Computer Science 7261, Springer. ISBN 978-3-642-34187-8. July 2012. No electronic version available. External information
Tim Blackmore, David Halliwell, Philip Barker, Kerstin Eder, Naresh Ramaram, Analysing and Closing Simulation Coverage by Automatic Generation and Verification of Formal Properties from Coverage Reports. 9th International Conference on Integrated Formal Methods (iFM). ISBN 978-3-642-30729-4, pp. 84–98. April 2012. No electronic version available. External information
Suleiman Abu Kharmeh, Kerstin Eder, David May, Complexity of Hardware Design and Model-Checking: An Asymptotic Analysis of State-Machine Metrics. CSTR-12-002, University of Bristol. March 2012. PDF, 598 Kbytes.
Charalambos Ioannides, Kerstin Eder, Coverage Directed Test Generation Automated by Machine Learning. ACM Transactions on Design Automation of Electronic Systems (TODAES), 17(1). ISSN 1084-4309, pp. 7:1–7:22. January 2012. No electronic version available. External information

2011

Charalambos Ioannides, Geoff Barrett, Kerstin Eder, Introducing XCS on Coverage Directed Test Generation. IEEE International High Level Design Validation and Test Workshop (HLDVT). ISBN 978-1-4577-1744-4, pp. 57–64. November 2011. No electronic version available. External information
Fangfang Yuan, Steve Wright, Kerstin Eder, David May, Managing Complexity Through Abstraction: A refinement-based approach to formalize Instruction Set Architectures. 13th International Conference on Formal Engineering Methods (ICFEM). ISBN 978-3-642-24558-9, pp. 585–600. October 2011. PDF, 473 Kbytes. External information
Elena Corina Grigore, Kerstin Eder, Alexander Lenz, Sergey Skachek, Anthony Pipe, Christopher Melhuish, Towards Safe Human-Robot Interaction. 12th Conference Towards Autonomous Robotic Systems (TAROS) 2011. ISBN 978-3-642-23231-2, pp. 323–335. September 2011. PDF, 414 Kbytes. External information
Suleiman Abu Kharmeh, Kerstin Eder, David May, A Design-for-Verification Framework for a Configurable Performance-Critical Communication Interface. Proceedings of the 9th International Conference on Formal Modeling and Analysis of Timed Systems, LNCS. ISBN 978-3-642-24309-7, pp. 335–351. August 2011. PDF, 303 Kbytes.
Charalambos Ioannides, Geoff Barrett, Kerstin Eder, XCS Cannot Learn All Boolean Functions. 13th Annual Genetic and Evolutionary Computation Conference (GECCO). ISBN 978-1-4503-0557-0, pp. 1283–1290. July 2011. No electronic version available.
Charalambos Ioannides, Geoff Barrett, Kerstin Eder, Improving XCS Performance on Overlapping Binary Problems. IEEE Congress on Evolutionary Computation (CEC). ISBN 978-1-4244-7834-7, pp. 1420–1427. June 2011. No electronic version available.
Elena Corina Grigore, Kerstin Eder, Alexander Lenz, Sergey Skachek, Anthony G. Pipe, Christopher Melhuish, Towards Safe Human-Robot Interaction. CSTR-11-002, University of Bristol. January 2011. PDF, 415 Kbytes.

2010

Charalambos Ioannides, Geoff Barrett, Kerstin Eder, Feedback-based Coverage Directed Test Generation: An industrial evaluation. HVC 2010. ISBN 978-3-642-19582-2, pp. 112–128. November 2010. PDF, 520 Kbytes.
Suleiman Abu Kharmeh, Kerstin Eder, David May, Formal Analysis of a Programmable Performance-Critical Processor Communication Interface. Proceedings of the 10th International Workshop on Automated Veriﬁcation of Critical Systems (AVoCS 2010). ISSN tbc, pp. 115–117. October 2010. PDF, 118 Kbytes. External information
Tim Blackmore, David Halliwell, Phil Barker, Kerstin Eder, Naresh Ramaram, Using a Formal Property Checker for Simulation Coverage Closure. Design Automation Conference. June 2010. No electronic version available. External information
Charalambos Ioannides, Kerstin Eder, Coverage Directed Test Generation automated by Machine Learning. CSTR-11-001, University of Bristol. March 2010. PDF, 550 Kbytes.
Steve Wright, Practical Experiences Constructing Working Virtual Machines. 09381 Extended Abstract Collection: Refinement Based Methods for the Construction of Dependable Systems - Dagstuhl Seminar. ISSN 1862-4405, pp. 173–177. January 2010. No electronic version available. External information
Steve Wright, Kerstin Eder, Using Event-B to construct Instruction Set Architectures. Formal Aspects of Computing, 23(1). ISSN 0934-5043, pp. 73–89. January 2010. No electronic version available. External information

2009

Steve Wright, Formal Construction of Instruction Set Architectures. PhD thesis. . December 2009. PDF, 1320 Kbytes.
Fangfang Yuan, Kerstin Eder, A Generic Instruction Set Architecture Model in Event-B for Early Design Space Exploration. CSTR-09-006, University of Bristol. September 2009. PDF, 272 Kbytes.
Jimson Mathew, A Jabir, H. Rahaman, Costas Argyrides, Dhiraj Pradhan, On the Synthesis of Bit-Parallel Galois Field Multipliers with On-line SEC and DED. , . July 2009. No electronic version available.
Steve Wright, MIDAS Machine Specification. , Department of Computer Science, University of Bristol. March 2009. PDF, 185 Kbytes.
Steve Wright, Automatic Generation of C from Event-B. Workshop on Integration of Model-based Formal Methods and Tools. February 2009. PDF, 170 Kbytes.

2008

Steve Wright, Using EventB to Create a Virtual Machine Instruction Set Architecture. Abstract State Machines, B and Z. ISBN 0302-9743/1611-3349, pp. 265–279. September 2008. PDF, 232 Kbytes. External information
Stephen Wright, Midas Design Document. CSTR-06-014, Department of Computer Science. April 2008. PDF, 144 Kbytes.
S. P. Mohanty, E. Kougianos, Simultaneous scheduling and binding for low gate leakage nano-complementary metal-oxide-semiconductor data path circuit behavioural synthesis. IET Computers & Digital Techniques (CDT), 2(2), pp. 118–`31. March 2008. PDF, 488 Kbytes.
H. Rahaman, Jimson Mathew, Dhiraj Pradhan, A. M. Jabir, C-Testable Bit Parallel Multipliers Over GF(2m). ACM Transactions on Design Automation of Electronic Systems (TODAES), . January 2008. No electronic version available.

2006

A. Jabir, Dhiraj Pradhan, Jimson Mathew, An Efficient Technique for Synthesis and Optimization of Polynomials in GF(2m). IEEE International Conference on Computer Aided Design. ISBN 1-59593-389-1, pp. 151–157. November 2006. No electronic version available.
H. Rahaman, Jimson Mathew, Dhiraj Pradhan, A.M. Jabir, Easily Testable Implementation for Bit Parallel Multipliers in GF(2m). IEEE International High Level Design Validation and Test Workshop(HLDVT). November 2006. No electronic version available.
Kerstin Eder, Peter Flach, Hsiou-Wen Hsueh, Towards Automating Simulation-Based Design Verification using ILP. 16th International Conference on Inductive Logic Programming. Stephen Muggleton, Ramon Otero, Alireza Tamaddoni-Nezhad, (eds.). ISBN 978-3-540-73846-6, pp. 154–168. August 2006. PDF, 352 Kbytes. External information
C. Liu, Z. Link, Dhiraj Pradhan, Reuse-Based Test Access and Integrated Test Scheduling for Network-on-Chip. Design, Automation and Test in Europe Conference and Exhibition. March 2006. PDF, 777 Kbytes.

2005

Kerstin Eder, Hsiou-Wen Hsueh, Towards Inducing Stimulus Generation Directives from Functional Coverage Data. CSTR-05-004, University of Bristol. June 2005. No electronic version available.
A. Jabir , Dhiraj Pradhan, An Efficient Graph Based Representation of Circuits and Calculation of Their Coefficients in Finite Field . Fourteenth International Workshop on Logic and Synthesis . June 2005. No electronic version available.

2004

S. Subbarayan, Dhiraj Pradhan, NIVER: Non Increasing Variable Elimination Resolution for Preprocessing SAT Instances. In Selected Revised Papers of International Conference on Theory and Applications of Satisfiability Testing Conference (Springer LNCS), , pp. 276–291. May 2004. PDF, 171 Kbytes.
Friedger Müffke, A Better Way to Design Communication Protocols. PhD thesis. University of Bristol. May 2004. PDF, 435 Kbytes.

2003

Dhiraj K Pradhan, Structural and Algebraic Coding Theory Based Approach to SAT Solvers. CSTR-03-003, Department of Computer Science, University of Bristol. March 2003. No electronic version available. External information

2002

Kerstin Eder, Geoff Barrett, Achieving Maximum Performance: A Method for the Verification of Interlocked Pipeline Control Logic. Proceedings of the 39th Design Automation Conference. ISBN 1-58113-461-4, pp. 135–140. June 2002. No electronic version available. External information

2000

D. Paul, M. Chatterjee, Dhiraj Pradhan, VERILAT: verification using logic augmentation and transformations. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, , 19(9). ISSN 0278-0070 , pp. 1041 – 1051 . September 2000. PDF, 294 Kbytes.

1996

Kunz, W. , Dhiraj Pradhan, Reddy, S.M. , A novel framework for logic verification in a synthesis environment. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, , 15(1). ISBN 0278-0070 , pp. 20–32. January 1996. PDF, 1473 Kbytes.