Publications on Computer Architecture

2013

Mike Huang, Jimson Mathew, Rishad Shafik, Subhasis Bhattacharjee, Dhiraj Pradhan, A Fast and Effective DFT for Test and Diagnosis of Power Switches in SOCs. Design, Automation, and Test in Europe (DATE) Conference. February 2013. No electronic version available.
Jimson Mathew, S.P.Mohanty, Dhiraj Pradhan, Attack Tolerant Cryptographic Hardware Design by Combining Error Correction and Uniform Switching Activity. Elsevier Journal of Electrical and Computer Engineering, . January 2013. No electronic version available.

2012

F. Balasa, Dhiraj Pradhan, Integrated Software Tools for the Memory Management of Low-Energy Embedded Signal Processing System. 5th International Congress on Image and Signal Processing (CISP 2012) . November 2012. PDF, 323 Kbytes.
Galadanci, J, Shafik, R.A, Jimson Mathew, Dhiraj Pradhan, A Closed-loop Control Strategy for Glucose Control in Artificial Pancreas Systems. In: IEEE Computer Society Intl. Symposium on Electronic Systems Design. October 2012. No electronic version available.
I. Sourdis, C. Strydis, C. Bouganis, B.Falsafi, Dhiraj Pradhan, Rishad Shafik, The DeSyRe project: on-Demand System Reliability (invited paper). 15th EUROMICRO Conference on Digital System Design (DSD),. September 2012. No electronic version available.
M. Poolakkaparambil, Jimson Mathew, A. M. Jabir, S. P. Mohanty, “Low Complexity Cross Parity Codes for Multiple and Random Bit Error Correction. 11th IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 141–146. September 2012. No electronic version available.
Jimson Mathew, Patra P., Dhiraj Pradhan, Kuttyamma, A.J, Eco-friendly Computing and Communication Systems. . ISBN 978-3-642-32111-5. August 2012. No electronic version available.
H Rahaman, Jimson Mathew, A. M. Jabir, Dhiraj Pradhan, VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF(2m)Using Dual Bases . Lecture note in Computer Science (LNCS) , Springer. ISSN 0302-9743, pp. 258–269. July 2012. No electronic version available.
S P Mohanty, J Singh, E. Kougianos, Dhiraj Pradhan, Statistical DOE-ILP based power-performance-process (P3) optimization of nano-CMOS SRAM. Integration, the VLSI Journal, 45( ), pp. 33–45. June 2012. PDF, 4827 Kbytes.
P. Yeolekar, R. A. Shafik, Jimson Mathew, Dhiraj Pradhan, S. P. Mohanty, “STEP: A Unified Design Methodology for Secure Test and IP Core Protection. 21st ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), , 2012 , pp. 333–338. May 2012. No electronic version available.
Philipp Grabher, Johann Großschädl, Simon Hoerder, Kimmo Järvinen, Dan Page, Stefan Tillich, Marcin Wójcik, An exploration of mechanisms for dynamic cryptographic instruction set extension. Journal of Cryptographic Engineering, 2(1). ISSN 2190-8516, pp. 1–18. May 2012. PDF, 282 Kbytes. External information
Jose Martinez Carranza, Andrew Calway, Efficient Visual Odometry Using a Structure-Driven Temporal Map. International Conference on Robotics and Automation (ICRA) . May 2012. PDF, 1833 Kbytes.
M. Poolakkaparambil,, Jimson Mathew, A. M. Jabir, S. P. Mohanty, Low Complexity Cross Parity Codes for Multiple and Random Bit Error Correction. 13th IEEE International Symposium on Quality Electronic Design (ISQED), pp. 57–62. March 2012. No electronic version available.
Suleiman Abu Kharmeh, Kerstin Eder, David May, Complexity of Hardware Design and Model-Checking: An Asymptotic Analysis of State-Machine Metrics. CSTR-12-002, University of Bristol. March 2012. PDF, 598 Kbytes.
L. Sun,, Jimson Mathew, Dhiraj Pradhan, S. P. Mohanty, “Enhanced Statistical Blockade Approaches for Fast Robustness Estimation and Compensation of Nano-CMOS Circuits. Journal of Low Power Electronics (JOLPE), 8(3), pp. 261–269. January 2012. No electronic version available.

2011

F. Balasa, Dhiraj Pradhan, Energy-Aware Memory Management for Embedded Multimedia Systems: A Computer-Aided Design Approach. Chapman & Hall / CRC Press. ISBN 1439814007/ 978-1439814000. December 2011. No electronic version available.
S. Banerjee, Jimson Mathew, S.P. Mohanty, Dhiraj Pradhan, M. Ciesielski, A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization. Journal of Low Power Electronics, 7(4), pp. 471–481. December 2011. No electronic version available.
Fangfang Yuan, Steve Wright, Kerstin Eder, David May, Managing Complexity Through Abstraction: A refinement-based approach to formalize Instruction Set Architectures. 13th International Conference on Formal Engineering Methods (ICFEM). ISBN 978-3-642-24558-9, pp. 585–600. October 2011. PDF, 473 Kbytes. External information
Tobias Vejda, Johann Groszschaedl, Dan Page, A Unified Multiply/Accumulate Unit for Pairing-Based Cryptography over Prime, Binary and Ternary Fields. Digital System Design, Architectures, Methods and Tools (DSD). ISBN 978-1-4577-1048-3, pp. 658–666. September 2011. No electronic version available.
Philipp Grabher, Johann Großschädl, Simon Hoerder, Kimmo Jarvinen, Dan Page, Stefan Tillich, Marcin Wojcik, An exploration of mechanisms for dynamic cryptographic instruction set extension. Cryptographic Hardware and Embedded Systems - CHES 2011. ISBN 978-3-642-23950-2, pp. 1–16. September 2011. PDF, 256 Kbytes. External information
M. Hosseinabady, R. Kakoee, Jimson Mathew, Dhiraj Pradhan, Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn Graph. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 99, pp. 1469 –1480. September 2011. PDF, 2054 Kbytes.
Philipp Grabher, Johann Großschädl, Simon Hoerder, Kimmo Jarvinen, Dan Page, Stefan Tillich, Marcin Wójcik, An Exploration of Mechanisms for Dynamic Cryptographic Instruction Set Extension. CSTR-11-004, Department of Computer Science, University of Bristol. August 2011. PDF, 237 Kbytes.
Billy Brumley, Dan Page, Bit-sliced binary normal basis multiplication. Symposium on Computer Arithmetic (ARITH), pp. 205–212. August 2011. No electronic version available.
Suleiman Abu Kharmeh, Kerstin Eder, David May, A Design-for-Verification Framework for a Configurable Performance-Critical Communication Interface. Proceedings of the 9th International Conference on Formal Modeling and Analysis of Timed Systems, LNCS. ISBN 978-3-642-24309-7, pp. 335–351. August 2011. PDF, 303 Kbytes.
Simon Hoerder, Marcin Wojcik, Stefan Tillich, Dan Page, An Evaluation of Hash Functions on a Power Analysis Resistant Processor Architecture. Workshop in Information Security Theory and Practice - WISTP 2011. ISBN 978-3-642-21039-6, pp. 160–174. June 2011. PDF, 301 Kbytes. External information
V. Misra, Jimson Mathew, Dhiraj Pradhan, Fault-tolerant De-Bruijn Graph Based Multipurpose Architecture and Routing Protocol for WSN. International Journal of Sensor Networks (IJSNet), . May 2011. No electronic version available.
Jimson Mathew, K. Maharatna, Dhiraj Pradhan, Pseudo-parallel Datapath Structure for Power Optimal Implementation of 128-pt FFT/IFFT for Wireless Personal Area Networks. Circuits, Systems, and Signal Processing, . ISBN ISSN: 0278-081X. April 2011. No electronic version available.
Mahesh P., Jimson Mathew, A.M. Jabir, Dhiraj Pradhan, S. P. Mohanty, BCH Code Based Multiple Bit Error Correction in Finite Field Multiplier Circuits. Proceedings of the 12th IEEE International Symposium on Quality Electronic Design (ISQED),. ISSN 29696771. March 2011. No electronic version available.
S. Banerjee, Jimson Mathew, Dhiraj Pradhan, A Routing-Aware ILS Design Technique. at IEEE Transactions on Very Large Scale Integration Systems , . ISSN 1063-8210. March 2011. No electronic version available.
S. Banerjee, Jimson Mathew, Dhiraj Pradhan, S.P. Mohanty, Variation-Aware TED- Based Approach for Nano-CMOS RTL Leakage Optimization. IEEE 24th International Conference on VLSI Design. ISSN 1063-8210. January 2011. No electronic version available.

2010

Stefan Tillich, Mario Kirschbaum, Alexander Szekely, SCA-Resistant Embedded Processors - The Next Generation. Twenty-Sixth Annual Computer Security Applications Conference, Austin, Texas, 6-10 December 2010, Proceedings. ISBN 978-1-4503-0133-6, pp. 211–220. December 2010. PDF, 924 Kbytes. External information
Jean-François Gallais, Johann Großschädl, Neil Hanley, Markus Kasper, Marcel Medwed, Francesco Regazzoni, Jörn-Marc Schmidt, Stefan Tillich, Marcin Wójcik, Hardware Trojans for Inducing or Amplifying Side-Channel Leakage of Cryptographic Software. Second Internation Conference on Trusted Systems (INTRUST), December 13-15, 2010, Beijing, China, Proceedings. ISBN 978-3-642-25282-2, pp. 253–270. December 2010. PDF, 351 Kbytes. External information
S. Mohanty, Dhiraj Pradhan, DOE-ILP Based Simultaneous Power and Read Stability Optimization in Nano-CMOS SRAM. Journal of Low Power Electronics, 6(3). October 2010. No electronic version available.
Onur Aciicmez, Billy Bob Brumley, Philipp Grabher, New Results on Instruction Cache Attacks. Cryptographic Hardware and Embedded Systems, CHES 2010. ISBN 978-3-642-15030-2, pp. 110–124. August 2010. No electronic version available.
H. Rahaman, Jimson Mathew, A. Jabir, Dhiraj Pradhan, Simplified Bit Parallel Systolic Multipliers for Special Class of GF(2m) with Testability. IET Computers and Digital Techniques, . July 2010. No electronic version available.
S.P. Mohanty, Dhiraj Pradhan, ULS: A Dual-Vth/High-K Nano-CMOS Universal Level Shifter for System-Level Power Management. ACM Journal of Emerging Technologies in Computing (JETC), 6(2), pp. 8:1-8–26. June 2010. No electronic version available.
G. Thakral, S. P. Mohanty, Dhiraj Pradhan, P3 (Power-Performance-Process) Optimization of Nano-CMOS SRAM using Statistical DOE-ILP. 11th IEEE International Symposium on Quality Electronic Design (ISQED). May 2010. No electronic version available.
Jimson Mathew, A Jabir, A.K Singh, H.Rahaman, Dhiraj Pradhan, A Galois Field Based Logic Synthesis Approach with Testability. IET Computers & Digital Techniques, . March 2010. No electronic version available.
G. Thakral, S. P. Mohanty, Dhiraj Pradhan, A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM. IEEE International Conference on VLSI Design (VLSID). January 2010. No electronic version available.
Steve Wright, Kerstin Eder, Using Event-B to construct Instruction Set Architectures. Formal Aspects of Computing, 23(1). ISSN 0934-5043, pp. 73–89. January 2010. No electronic version available. External information

2009

Philipp Grabher, Johann Groszschaedl, Dan Page, Non-Deterministic Processors: FPGA-based Analysis of Area, Performance and Security. Embedded Systems Security (WESS), pp. 1–10. December 2009. No electronic version available.
H. Rahaman, Jimson Mathew, Dhiraj Pradhan, Test Generation in Systolic Architecture for Multiplication over GF(2^m). IEEE Transactions on VLSI Systems, . November 2009. No electronic version available.
Fangfang Yuan, Kerstin Eder, A Generic Instruction Set Architecture Model in Event-B for Early Design Space Exploration. CSTR-09-006, University of Bristol. September 2009. PDF, 272 Kbytes.
D. Maslov, Jimson Mathew, D. Cheung, Dhiraj Pradhan, AN O(m2)-DEPTH QUANTUM ALGORITHM FOR THE ELLIPTIC CURVE DISCRETE LOGARITHM PROBLEM OVER GF(2^m). Journal of Quantum Information & Computation, 9(7), pp. 0610–0627. July 2009. No electronic version available.
H. Rahaman, Jimson Mathew, A. K Singh, Dhiraj Pradhan, Transition Fault Detection in Bit Parallel Multipliers over GF(2^m). Transactions on Circuits and Systems, . May 2009. No electronic version available.
Steve Wright, MIDAS Machine Specification. , Department of Computer Science, University of Bristol. March 2009. PDF, 185 Kbytes.
Costas Argyrides, Carlos Lisboa, Ahmad Al Yamani, Luigi Carro, Dhiraj Pradhan, Increasing Memory Yield in Future Technologies through Innovative Design. IEEE International Symposium on Quality Electronic Design. (ISQED 09) . March 2009. No electronic version available.
Costas Argyrides, Carlos Arthur Lisboa, Luigi Carro, Dhiraj Pradhan, Minimizing the Recomputation Time in Soft Error Tolerant Matrix Multiplication Algorithms. 1st HiPEAC Workshop on Design for Reliability (DFR’09). January 2009. No electronic version available.

2008

Jimson Mathew, R. Mahesh, A.P Vinod, L. Edmund, Realization of Low Power High-Speed Channel Filters with Stringent Adjacent Channel Attenuation. IEICE Trasactions, . December 2008. No electronic version available.
Övünc Kocabas, Erkay Savas, Johann Großschädl, Enhancing an Embedded Processor Core with a Cryptographic Unit for Performance and Security. Proceedings of the 4th International Conference on Reconfigurable Computing and FPGAs (ReConFig 2008), pp. 409–414. December 2008. PDF, 169 Kbytes.
Jawar Singh, Dhiraj Pradhan, Simon Hollis, Saraju Mohanty, A Single Ended 6T SRAM Cell Design for Ultra-Low-Voltage Applications . IEICE Electronics Express, 5(18). ISSN 1349-2543, pp. 750–755. September 2008. PDF, 1109 Kbytes. External information
Steve Wright, Using EventB to Create a Virtual Machine Instruction Set Architecture. Abstract State Machines, B and Z. ISBN 0302-9743/1611-3349, pp. 265–279. September 2008. PDF, 232 Kbytes. External information
M. Hosseinabady, R. Kakoee, Jimson Mathew, Dhiraj Pradhan, De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs. Proceedings of the conference on Design, automation and test in Europe (DATE 2008), pp. 1370–1273. August 2008. PDF, 142 Kbytes.
Philipp Grabher, Johann Großschädl, Dan Page, On Software Parallel Implementation of Cryptographic Pairings. Selected Areas in Cryptography --- SAC 2008, pp. 34–49. August 2008. No electronic version available.
Philipp Grabher, Johann Großschädl, Dan Page, Light-Weight Instruction Set Extensions for Bit-Sliced Cryptography. Cryptographic Hardware and Embedded Systems --- CHES 2008, pp. 331–345. August 2008. PDF, 247 Kbytes.
Johann Großschädl, Tobias Vejda, Dan Page, Reassessing the TCG Specifications for Trusted Computing in Mobile and Embedded Systems. Proceedings of the 1st IEEE Workshop on Hardware-Oriented Security and Trust (HOST 2008), pp. 84–90. June 2008. PDF, 224 Kbytes.
Joshi, Dhiraj Pradhan, Jack Stifler, Fault-Tolerant Computing. John Wiley & Sons. June 2008. No electronic version available. External information

2007

Philipp Grabher, Johann Großschädl, Dan Page, Cryptographic Side-Channels from Low-Power Cache Memory. Cryptography and Coding, pp. 170–184. December 2007. No electronic version available.
M. Hosseinabady, M. Reza, Jimson Mathew, Dhiraj Pradhan, Reliable Network-on-Chip Based on Generalized de Bruijn Graph. IEEE International High Level Design Validation and Test Workshop (HLDVT) (to appear). November 2007. No electronic version available.
Stefan Tillich, Johann Großschädl, Power Analysis Resistant AES Implementation with Instruction Set Extensions. Cryptographic Hardware and Embedded Systems --- CHES 2007, pp. 303–319. September 2007. No electronic version available.
B. R. Jose, Jimson Mathew, P. Mythili, Dhiraj Pradhan, A Triple-Mode Feed-Forward Sigma-Delta Modulator Design For GSM / WCDMA / WLAN Applications. 20th IEEE International System On Chip Conference (IEEE SOCC 2007), September 2007. . September 2007. No electronic version available.
A. M. Jabir, Dhiraj Pradhan, Raja Thiruchi Loganthan, A. Singh, A Technique for Representing Multiple Output Binary Functions with Applications to Verification and Simulation . IEEE Transactions on Computers, 56(8). ISBN ISSN: 0018-9340, pp. 1133–1145. August 2007. PDF, 3746 Kbytes.
A.M Jabir, Dhiraj Pradhan, A Graph-Based Unified Technique for Computing and Representing Coefficients over Finite Fields . IEEE Transactions on Computers, 56(8). ISBN ISSN: 0018-9340, pp. 1119–1132. August 2007. PDF, 4546 Kbytes.
Tobias Vejda, Dan Page, Johann Großschädl, Instruction Set Extensions for Pairing-Based Cryptography. Pairing-Based Cryptography --- PAIRING 2007, pp. 208–224. July 2007. PDF, 306 Kbytes.
Jimson Mathew, H. Rahaman, Dhiraj Pradhan, Efficient Testable Bit Parallel Multipliers over GF(2^m) with Constant Test Set. 13th IEEE International On-Line Testing Symposium,Greece. June 2007. No electronic version available.
Peter Leadbitter, Dan Page, Nigel Smart, Non-deterministic Multi-threading. IEEE Transactions on Computers, 56(7), pp. 992–998. June 2007. No electronic version available.
H. Zarandi, S. G. Miremadi, Dhiraj Pradhan, Jimson Mathew, CAD-Directed SEU Susceptibility Reduction in FPGA Circuits Designs. IEEE International Conference on Circuits and Systems, (ISCAS 2007), USA. May 2007. No electronic version available.
H. Zarandi, S. G. Miremadi, Dhiraj Pradhan, Jimson Mathew, Soft Error Mitigation in Switch Modules of SRAM-Based FPGAs. IEEE International Conference on Circuits and Systems, (ISCAS 2007), USA. May 2007. No electronic version available.
R. Stapenhurst, Koushik Maharatna, Jimson Mathew, J. Nunez-Yanez, Dhiraj Pradhan, On the Hardware Reduction of z-Datapath of Vectoring CORDIC. IEEE International Conference on Circuits and Systems, (ISCAS 2007), USA. May 2007. No electronic version available.
M. Hosseinabady, Jimson Mathew, Dhiraj Pradhan, Application of de Bruijn graphs to NoC design. Design Automation and Test in Europe Workshops, DATE07-WKS , pp. 111–116. March 2007. No electronic version available.
H. Rahaman, Jimson Mathew, Dhiraj Pradhan, Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m). Chapter in VLSI Design, 2007, pp. 479–484. January 2007. No electronic version available.

2006

Costas Argyrides, Jimson Mathew, Ahmad Al-Yamani, Dhiraj Pradhan, Performance Analysis of an Error Tolerant Low Power Memory Architecture. IEEE International Design and Test Workshop. November 2006. PDF, 333 Kbytes.
Simon Hollis, Simon W. Moore, RasP: An Area-efficient, On-chip Network. 24th International Conference on Computer Design (ICCD). October 2006. PDF, 186 Kbytes.
David May, CSPIC - a Low-power Microcontroller. CSTR-06-011, University of Bristol, UK. August 2006. No electronic version available.
Jimson Mathew, Koushik Maharatna, Dhiraj Pradhan, A Low Power 128-Pt Implementation of FFT/IFFT for High Performance Wireless Personal Area Networks. IEEE PRIME Conference, pp. 377–380. June 2006. No electronic version available.
Simon Hollis, S. W. Moore, An area-efficient, pulse-based interconnect. IEEE International Symposium on Circuits and Systems (ISCAS). May 2006. PDF, 128 Kbytes.
Douglas Watt, David May, A Language and Processor for Unifying System-on-Chip Design. CSTR-06-010, University of Bristol, UK. April 2006. No electronic version available.
Jimson Mathew, Koushik Maharatna, Dhiraj Pradhan, Exploration of Power optimal Implementation Technique of 128-Pt FFT/IFFT for WPAN using Pseudo- Parallel Datapath Strcuture. IEEE International Conference on Communication Systems, Singapore. February 2006. No electronic version available.
Simon Hollis, Simon W. Moore, An Asynchronous Interconnect Architecture for Device Security Enhancement. 19th International Conference on VLSI Design. ISBN 0-7695-2502-4, pp. 209–215. January 2006. PDF, 169 Kbytes.

2005

S.Chidambaram, D. Kagaris, Dhiraj Pradhan, Comparative Study of CA with Phase Shifters and GLFSRs. International Test Conference 2005. November 2005. No electronic version available.
P. Grabher, D. Page, Hardware Acceleration of the Tate Pairing in Characteristic Three. , Department of Computer Science, University of Bristol. August 2005. PDF, 161 Kbytes.
Dhiraj Pradhan, Chunsheng Liu, EBIST: A Novel Test Generator with Built-in fault Detection Capability. ieeetcad, 24(8). August 2005. PDF, 354 Kbytes.
P. Grabher, D. Page, Hardware Acceleration of the Tate Pairing in Characteristic Three. Cryptographic Hardware and Embedded Systems (CHES - 2005), pp. 398–411. August 2005. No electronic version available.
Robert Granger, Dan Page, Martijn Stam, Hardware and Software Normal Basis Arithmetic for Pairing-Based Cryptography in Characteristic Three. IEEE Transactions on Computers, 54(7), pp. 852–860. July 2005. No electronic version available.
Dhiraj Pradhan, D. Kagaris , A Hamming Distance Based Test Pattern Generator With Improved Fault Coverage. IEEE International On-Line Testing Symposium. June 2005. PDF, 130 Kbytes.

2004

T.L. Rajaprabhu, A.K. Singh, A.M. Jabir, Dhiraj Pradhan, MODD for CF: a representation for fast evaluation of multiple-output functions. Ninth IEEE International High-Level Design Validation and Test Workshop, 2004. . ISSN 1552-6674 , pp. 61–66. November 2004. PDF, 2043 Kbytes.
Chunsheng Liu Cota, Sharif, H, Dhiraj Pradhan, Test scheduling for network-on-chip with BIST and precedence constraints. International Test Conference, 2004. Proceedings. , pp. 1369 –1378. November 2004. PDF, 962 Kbytes.
Jorge Buenabad-Chavez, Henk L Muller, Paul W A Stallard, David H D Warren, The diffusion space of data diffusion architectures. Parallel Computing, 30(11). ISSN 0167-8191, pp. 1169–1193. November 2004. PDF, 296 Kbytes.
S. Subbarayan, Dhiraj Pradhan, NiVER: Non Increasing Variable Elimination Resolution. Proceedings of The Seventh International Conference on Theory and Applications of Satisfiability Testing (SAT '04), pp. 351–356. May 2004. PDF, 179 Kbytes.
Bhattacharjee, S, Dhiraj Pradhan, LPRAM: a novel low-power high-performance RAM design with testability and scalability. ieeetcad, 23(5). ISSN 0278-0070 , pp. 637–651. May 2004. PDF, 492 Kbytes.
A.M. Jabir, Dhiraj Pradhan, MODD: a new decision diagram and representation for multiple output binary functions. Design, Automation and Test in Europe Conference and Exhibition, 2004. ISSN 1530-1591 , pp. 1388 –1389. February 2004. PDF, 221 Kbytes.

2003

Dhiraj Pradhan, Logic transformation and coding theory-based frameworks for Boolean satisfiability. Eighth IEEE International High-Level Design Validation and Test Workshop, 2003. . ISBN 0-7803-8236-6, pp. 57–62. December 2003. PDF, 342 Kbytes.
Dhiraj Pradhan, Askar, S. , Ciesielski, M. , Mathematical framework for representing discrete functions as word-level polynomials. Eighth IEEE International High-Level Design Validation and Test Workshop, 2003. ISBN INSPEC Accession Number:790724, pp. 135–139. December 2003. PDF, 205 Kbytes.
Dhiraj Pradhan, Askar, S, Ciesielski, M, Mathematical framework for representing discrete functions as word-level polynomials. Eighth IEEE International High-Level Design Validation and Test Workshop, 2003. ISSN 1552-6674, pp. 135–139. December 2003. PDF, 205 Kbytes.
Mitrajit Chatterjee , Dhiraj Pradhan, A BIST pattern generator design for near-perfect fault coverage. ieeetc, 52(12). ISSN 0018-9340 , pp. 1543 –1558 . December 2003. PDF, 580 Kbytes.
D. Page, J. Irwin, Using Media Processors for Low-Memory AES Implementation. 14th International Conference on Application-specific Systems, Architectures and Processors (ASAP). E. Deprettere, S. Bhattacharyya, J. Cavallaro, A. Darte, L. Thiele , (eds.). ISBN 0-7695-1992-X, pp. 144–154. June 2003. No electronic version available.
Dhiraj Pradhan, Chunsheng Liu , Chakraborty, K, EBIST: a novel test generator with built-in fault detection capability. Design, Automation and Test in Europe Conference and Exhibition, 2003 . ISSN 1530-1591 , pp. 224–229. May 2003. PDF, 296 Kbytes.
Ganesan, E., Dhiraj Pradhan, Wormhole routing in de Bruijn networks and hyper-de Bruijn networks. International Symposium on Circuits and Systems, 2003. . May 2003. PDF, 283 Kbytes.
D. Page, Defending Against Cache Based Side-Channel Attacks. Information Security Technical Report, 8(1). ISSN 1363-4127, pp. 30–44. April 2003. No electronic version available.
J. Irwin, H. L. Muller, D. Page, N. P. Smart, B. W. Silverman, Probabilistic Instruction Execution: The MAYBE Predicate. CSTR-03-005, Department of Computer Science, University of Bristol. March 2003. PDF, 85 Kbytes.
D. Page, N. P. Smart, Hardware Implementation of Finite Fields of Characteristic Three. Cryptographic Hardware and Embedded Systems (CHES). B. S. Kaliski Jr., C. K. Koc, C. Paar, (eds.). ISSN 0302-9743, pp. 529–539. February 2003. No electronic version available.

2002

J. Irwin, D. Page, N. P. Smart, Instruction Stream Mutation for Non-Deterministic Processors. 13th International Conference on Application-specific Systems, Architectures and Processors (ASAP). M. Shulte, S. Bhattacharyya, N. Burgess, R. Schreiber, (eds.). ISBN 0-7695-1712-9, pp. 286–295. July 2002. PDF, 103 Kbytes.
J. Irwin, D. May, H. L. Muller, D. Page, Predictable Instruction Caching for Media Processors. 13th International Conference on Application-specific Systems, Architectures and Processors (ASAP). M. Shulte, S. Bhattacharyya, N. Burgess, R. Schreiber, (eds.). ISBN 0-7695-1712-9, pp. 141–150. July 2002. PDF, 70 Kbytes.
D. Page, Theoretical Use of Cache Memory as a Cryptanalytic Side-Channel. CSTR-02-003, Department of Computer Science, University of Bristol. June 2002. PDF, 183 Kbytes.
Daniel William Towner, The Uniform Heterogeneous Multi-threaded Processor Architecture. PhD thesis. Department of Computer Science, University of Bristol. April 2002. PDF, 1259 Kbytes.
Henk Muller, Dan Page, James Irwin, David May, Caches with Compositional Performance. Chapter in Embedded Processor Design Challenges. Ed F Deprette, Jurgen Teich, Stamasis Vassiliadis, (eds.). ISBN 3-540-43322-8, pp. 242–259. February 2002. PDF, 225 Kbytes.

2001

J. Irwin, D. Page, N. P. Smart, Instruction Stream Mutation for Non-Deterministic Processors. CSTR-01-008, Department of Computer Science, University of Bristol. December 2001. PDF, 120 Kbytes.
D. Page, N. Sidwell, A Fetch Resident Split Jump Mechanism for Non-Deterministic Processors. CSTR-01-007, Department of Computer Science, University of Bristol. December 2001. PDF, 46 Kbytes.
D. Page, Effective Use of Partitioned Cache Memories. PhD thesis. Department of Computer Science, University of Bristol. November 2001. No electronic version available.
Cliff Randell, Henk Muller, The eSleeve: An Arm Mounted Wearable Computing System. CSTR-01-002, Department of Computer Science, University of Bristol. November 2001. PDF, 501 Kbytes.
Daniel Towner, David May, The `Uniform Heterogeneous Multi-threaded' Processor Architecture. Communicating Process Architectures -- 2001. Alan Chalmers, Majid Mirmehdi, Henk Muller, (eds.). ISBN 1 58603 202, pp. 103–116. September 2001. PDF, 106 Kbytes.
Dhiraj Pradhan, Logic insertion to speed-up logic verification: a recent development. Seventh International On-Line Testing Workshop, 2001. Proceedings. , pp. 61–64. July 2001. PDF, 254 Kbytes.
David May, Henk L. Muller, Nigel P. Smart, Non-deterministic Processors. Information Security and Privacy. V. Varadharajan, Y. Mu, (eds.). ISBN 3-540-42300-1, pp. 115–129. July 2001. No electronic version available. External information
D. May, H. L. Muller, N. P. Smart, Random Register Renaming to Foil DPA. Cryptographic Hardware and Embedded Systems - CHES 2001. C. K. Koc, D. Naccache, C. Paar, (eds.). ISBN 3-540-42521-7, pp. 28–38. May 2001. No electronic version available. External information

2000

David May, James Irwin, Henk L Muller, Dan Page, Effective Caching for Multithreaded Processors. Communicating Process Architectures 2000. P. H. Welch, A. W. P. Bakkers, (eds.), pp. 145–154. September 2000. PDF, 75 Kbytes.
Shondip Sen, Henk Muller, David May, Synchronisation in a Multithreaded Processor. Communicating Process Architectures 2000. P. H. Welch, A. W. P. Bakkers, (eds.). ISBN 1 58603 077 9, pp. 137–144. September 2000. PDF, 45 Kbytes.
David May, Henk Muller, Shondip Sen, Hardware Migratable Channels. Euro-Par 2000 Parallel Processing. ISBN 3-540-67956-1, pp. 545–549. September 2000. PDF, 136 Kbytes.
David May, Henk Muller, Cache Memory. Patent. WO045269. August 2000. No electronic version available. External information
N Sidwell, Expansion of data. Patent. US6100905. August 2000. No electronic version available. External information
N Sidwell, A Sturges, A computer system for executing branch instructions. Patent. EP1003095. May 2000. No electronic version available. External information
David May, Henk Muller, Shondip Sen, Hardware Migratable Channels. CSTR-00-005, Department of Computer Science, University of Bristol. March 2000. PDF, 70 Kbytes.
Chatterjee, M. , Banerjee, S. , Dhiraj Pradhan, Buffer assignment algorithms on data driven ASICs. IEEE Transactions on Computers, , 49(1). ISBN 0018-9340 , pp. 16–32. January 2000. PDF, 518 Kbytes.

1999

David May, Andy Sturges, Nathan Sidwell, System and method for addressing plurality of data values with a single address in a multi-value store on FIFO basis . Patent. US6009508. December 1999. No electronic version available. External information
David May, Andrew Jones, Microcomputer with interrupt packets. Patent. EP953913. November 1999. No electronic version available. External information
David May, Andrew Jones, Microcomputer with bit packets for interrupts, control and memory access. Patent. EP953914. November 1999. No electronic version available. External information
David May, Andrew Jones, Microcomputer with packet translation for event packets and memory access packets. Patent. EP953915. November 1999. No electronic version available. External information
David May, Andrew Jones, Packet distribution in a microcomputer. Patent. EP959411. November 1999. No electronic version available. External information
David May, Andrew Jones, Interrupt and control packets for a microcomputer. Patent. EP959412. November 1999. No electronic version available. External information
N Sidwell, A Sturges, Split branch system utilizing separate set branch, condition and branch instructions and including dual instruction fetchers . Patent. US5961637. October 1999. No electronic version available. External information
David May, Andrew Jones, Microcomputer chips with interconnected address and data paths. Patent. EP953916. September 1999. No electronic version available. External information
Proceedings of the Fifteenth Annual UK Performance Engineering Workshop. J Bradley, N Davies, (eds.). Department of Computer Science, University of Bristol. ISSN 0952402785. July 1999. No electronic version available. External information
N Davies, J Holyer, P Thompson, End-to-End Management of Mixed Applications Across Networks. CSTR-99-008, Department of Computer Science, University of Bristol. May 1999. No electronic version available.
N Sidwell, Computer and a method of operating a computer to combine data values within a singularly addressable data string. Patent. US5884069. March 1999. No electronic version available. External information
N Sidwell, C Barnaby, Method for transposing multi-bit matrix wherein first and last sub-string remains unchanged while intermediate sub-strings are interchanged. Patent. US5875355. February 1999. No electronic version available. External information
Colin J. Burgess, Alan G. Chalmers, Optimisation of irregular multiprocessor computer architectures using genetic algorithms. Annals of Operations Research, 86 (1999). ISSN 0254-5330, pp. 239–257. February 1999. PDF, 211 Kbytes.
N Sidwell, Arithmetic unit . Patent. US5859789. January 1999. No electronic version available. External information
N Sidwell, Replication of data. Patent. US05859790. January 1999. No electronic version available. External information
David May, Andrew Sturges, A cache system. Patent. EP890149. January 1999. No electronic version available. External information

1998

N Sidwell, System and method for restructuring data strings . Patent. US5822619. October 1998. No electronic version available. External information
Henk Muller, David May, James Irwin, Dan Page, Novel Caches for Predictable Computing. CSTR-98-011, Department of Computer Science, University of Bristol. October 1998. PDF, 90 Kbytes.
David May, Dan Page, James Irwin, Henk L Muller, Microcaches. CSTR-98-010, Department of Computer Science, University of Bristol. October 1998. PDF, 113 Kbytes.
David May, Glenn Farrell, Andrew Sturges, Bruno Fel, Catherine Barneby, A cache system. Patent. EP856798. August 1998. No electronic version available. External information
David May, Andrew Sturges, A cache system for concurrent processes. Patent. EP856797. August 1998. No electronic version available. External information
Neil Pollard, David May, Using Interval Arithmetic to Calculate Data Sizes for Compilation to Multimedia Instruction Sets. ACM Multimedia '98. ISBN 1-58113-036-8, pp. 279–284. August 1998. No electronic version available. External information
Jorge Buenabad-Chavez, Virtual Memory on Data Diffusion Architectures. PhD thesis. Department of Computer Science, University of Bristol. July 1998. PDF, 904 Kbytes.
Neil Pollard, David May, Using Interval Arithmetic to Calculate Data Sizes for Compilation to Multimedia Instruction Sets. CSTR-98-004, Department of Computer Science, University of Bristol. February 1998. PDF, 204 Kbytes.
David May, Henk L. Muller, Using Channels for Multimedia Communication. CSTR-98-002, Department of Computer Science, University of Bristol. February 1998. PDF, 52 Kbytes.
Henk L. Muller, David May, A Simple Protocol to Communicate Channels over Channels. CSTR-98-001, Department of Computer Science, University of Bristol. January 1998. PDF, 168 Kbytes.

1997

David May, Brian Parsons, Peter Thompson, Christopher Walker, A communications device.. Patent. EP611014. October 1997. No electronic version available. External information
David May, Brian Parsons, Peter Thompson, Christopher Walker, Message Routing. Patent. EP405990. September 1997. No electronic version available. External information
David May, Peter Thompson, Brian Parsons, Christopher Walker, Message Routing. Patent. EP405989. January 1997. No electronic version available. External information

1996

Bowen, N.S, Dhiraj Pradhan, The effect of program behavior on fault observability. , IEEE Transactions on Computers, 45(8). ISSN 0018-9340 , pp. 868–880. August 1996. PDF, 1422 Kbytes.
Chakradhar, S.T., Banerjee, S., Roy, R.K., Dhiraj Pradhan, Synthesis of initializable asynchronous circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, , 4(2). ISSN 1063-8210 , pp. 254–263. June 1996. PDF, 1182 Kbytes.
David May, Jonathan Edwards, David Waller, Microcomputer with high density RAM in separate isolation well on single chip. Patent. US5506437. April 1996. No electronic version available. External information
Henk L. Muller, Paul W. A. Stallard, David H. D. Warren, Implementing the Data Diffusion Machine using Crossbar Routers. Proceedings of the 10th International Parallel Processing Symposium. ISBN 0-8186-7255-2, pp. 152–158. April 1996. PDF, 93 Kbytes.
David May, Jonathan Edwards, David Waller, Microcomputer with high density ram in separate isolation well on single chip. Patent. US5491359. February 1996. No electronic version available. External information
David May, Brian Parsons, Peter Thompson, Christopher Walker, Apparatus providing addressable storage locations as virtual links and storing predefined destination information for any messages transmitted on virtual links at these locations. Patent. US5495619. February 1996. No electronic version available. External information
Henk L. Muller, Paul W. A. Stallard, David H. D. Warren, Multitasking and Multithreading on a Multiprocessor with Virtual Shared Memory. Proceedings of the 2nd International Symposium on High-Performance Computer Architecture. ISBN 0-8186-7237-4, pp. 212–221. February 1996. PDF, 79 Kbytes.
Henk L. Muller, Paul W. A. Stallard, David H. D. Warren, The Role of Associative Memory in VSM Architectures: A Price-Performance Comparison. Proceedings of 4th EUROMICRO Workshop on Parallel and Distributed Processing. ISBN 0-8186-7376-1, pp. 41–49. January 1996. No electronic version available.

1995

Henk L. Muller, Paul W. A. Stallard, David H. D. Warren, Hiding Miss Latencies with Multithreading on the Data Diffusion Machine. Proceedings of the 1995 International Conference on Parallel Processing, ICPP'95, Volume I. ISBN 0-8493-2615-X, pp. 178–185. August 1995. PDF, 82 Kbytes.
Henk L. Muller, Paul W. A. Stallard, David H. D. Warren, The Application of Skewed-Associative Memories to Cache Only Memory Architectures. Proceedings of the 1995 International Conference on Parallel Processing, ICPP'95, Volume I . ISBN 0-8493-2615-X, pp. 150–154. August 1995. PDF, 53 Kbytes.
Henk L. Muller, Paul W. A. Stallard, David H. D. Warren, The Role of Associative Memory in VSM Architectures: A Price-Performance Comparison. CSTR-95-009, Department of Computer Science, University of Bristol. May 1995. PDF, 100 Kbytes.

1994

Henk L. Muller, Paul W. A. Stallard, David H. D. Warren, An Evaluation Study of a Link-Based Data Diffusion Machine. Proceedings of theInternational Workshop on Support for Large Scale Shared Memory Architectures, pp. 115–128. April 1994. PDF, 133 Kbytes.
Henk L. Muller, Paul W. A. Stallard, David H. D. Warren, Sanjay Raina, Parallel Evaluation of a Parallel Architecture by means of Calibrated Emulation. Proceedings of the 8th International Parallel Processing Symposium. ISBN 0-8186-5602-6, pp. 260–267. April 1994. PDF, 80 Kbytes.

1993

Paul W. A. Stallard, Henk L. Muller, David H. D. Warren, Performance Evaluation of Parallel Programs on the Data Diffusion Machine. Performance Evaluation of Parallel Systems, PEPS '93, pp. 94–101. November 1993. PDF, 75 Kbytes.
Henk L. Muller, Paul W. A. Stallard, David H. D. Warren, The Data Diffusion Machine with a Scalable Point-to-Point Network. CSTR-93-17, Department of Computer Science, University of Bristol. October 1993. PDF, 131 Kbytes.
Sanjay Raina, Emulation of a Virtual Shared Memory Architecture. PhD thesis. Department of Computer Science, University of Bristol. September 1993. PDF, 1057 Kbytes.
Henk Muller, Simulating Computer Architectures. PhD thesis. University of Amsterdam. February 1993. PDF, 560 Kbytes.