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Efficient online testing of an array of reconfigurable RISC Processors

S. Pagliarini , S. Pontarelli , Jimson Mathew, I. Sourdis , D. A. Khan A. Malek , S. Tzilis, G. Smaragdos , C. Strydis, Dhiraj Pradhan, Efficient online testing of an array of reconfigurable RISC Processors. Chapter in Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN’15), Grenoble, France, 13 March 2015. March 2015. No electronic version available.

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