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a??STEP: A Unified Design Methodology for Secure Test and IP Core Protection

P. Yeolekar, R. A. Shafik, Jimson Mathew, Dhiraj Pradhan, S. P. Mohanty, a??STEP: A Unified Design Methodology for Secure Test and IP Core Protection. 21st ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), , 2012 , pp. 333–338. May 2012. No electronic version available.

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