A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization
S. Banerjee,
Jimson Mathew, S.P. Mohanty,
Dhiraj Pradhan, M. Ciesielski,
A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization.
Journal of Low Power Electronics, 7(4), pp. 471–481. December 2011. No electronic version available.
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