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Hardware Implementations of the Round-Two SHA-3 Candidates: Comparison on a Common Ground

Stefan Tillich, Martin Feldhofer, Mario Kirschbaum, Thomas Plos, J??rn-Marc Schmidt, Alexander Szekely, Hardware Implementations of the Round-Two SHA-3 Candidates: Comparison on a Common Ground. Proceedings of Austrochip 2010, Villach, Austria, October 6, 2010. ISBN 978-3-200-01945-4, pp. 43–48. October 2010. PDF, 281 Kbytes. External information

Abstract

Hash functions are a core part of many protocols that are in daily use. Following recent results that raised concerns regarding the security of the current hash standards, the National Institute of Standards and Technology (NIST) pronounced a competition to find a new Secure Hash Algorithm (SHA), the SHA-3. An important criterion for the new standard is not only its security, but also the performance and the costs of its implementations. This paper evaluates all 14 candidates that are currently in the second round of the SHA-3 competition. We provide a common framework that allows a fair comparison of the hardware implementations of all SHA-3 candidates. We optimized the hardware modules towards maximum throughput and give concrete numbers of our implementations for a 0.18 I?m standard-cell technology.

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