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Error Tolerant Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m),

A.K Singh, A Bera, H. Rahaman, Jimson Mathew, Dhiraj Pradhan, Error Tolerant Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m),. International Journal of Electronic Science and Technology, . July 2009. No electronic version available.

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