In this paper we present two polynomial time-complexity heuristic algorithms for optimization of gate-oxide leakage (tunneling current) during behavioral synthesis through simultaneous scheduling and binding. One algorithm considers the time-constraint explicitly and the other considers it implicitly while both account for resource constraints. The algorithms selectively bind the off-critical operations to instances of the pre-characterized resources consisting of transistors of higher oxide thickness, and critical operations to the resources of lower oxide thickness for power and performance optimization. We design and characterize functional and storage units of different gateoxide thicknesses and built a datapath library. Extensive experiments for several behavioral synthesis benchmarks for 45nm CMOS technology showed that reduction as high as 85% can be obtained.