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An Asynchronous Interconnect Architecture for Device Security Enhancement

Simon Hollis, Simon W. Moore, An Asynchronous Interconnect Architecture for Device Security Enhancement. 19th International Conference on VLSI Design. ISBN 0-7695-2502-4, pp. 209–215. January 2006. PDF, 169 Kbytes.

Abstract

We present a new style of long-distance, on-chip interconnect, based loosely on the asynchronous GasP architecture. It has a number of advantages over conventional designs, the most prominent being security enhancements, a reduction in the number of wires required, no need for clock distribution or packetization, and ease of composition. We give some sample throughput and latency figures from simulation on a 0.18 m technology and show that it is viable for use with modern interconnect requirements, is of low complexity and has a lower area requirement than parallel interconnect over distances as short as 1mm.

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