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An area-efficient, pulse-based interconnect

Simon Hollis, S. W. Moore, An area-efficient, pulse-based interconnect. IEEE International Symposium on Circuits and Systems (ISCAS). May 2006. PDF, 128 Kbytes.


We present a new style of long-distance, on-chip interconnect based loosely on the asynchronous GasP architecture, with a number of advantages over conventional interconnect. Most signi cant are a low wire count, a low area requirement, the absence of a global clock and simple composition with existing designs. We give some sample throughput and latency gures from simulation on a 0.18 m technology, and show that it is viable for use with modern interconnect requirements, is of low complexity, and has a lower area requirement than parallel interconnect over distances as short as 1mm.

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