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A Technique for Representing Multiple Output Binary Functions with Applications to Verification and Simulation

A. M. Jabir, Dhiraj Pradhan, Raja Thiruchi Loganthan, A. Singh, A Technique for Representing Multiple Output Binary Functions with Applications to Verification and Simulation . IEEE Transactions on Computers, 56(8). ISBN ISSN: 0018-9340, pp. 1133–1145. August 2007. PDF, 3746 Kbytes.

Abstract

This paper presents a technique for representing multiple output binary and word-level functions in GF(N) ($N=p^m$, p a prime number and m a nonzero positive integer) based on decision diagrams (DD). The presented DD is canonical and can be made minimal with respect to a given variable order. The DD has been tested on benchmarks including integer multiplier circuits and the results show that it can produce better node compression (more than an order of magnitude in some cases) compared to shared BDDs. The benchmark results also reflect the effect of varying the input and output field sizes on the number of nodes. Methods of graph-based representation of characteristic and encoded characteristic functions in GF(N) are also presented. Performance of the proposed representations has been studied in terms of average path lengths and the actual evaluation times with 50,000 randomly generated patterns on many benchmark circuits. All these results reflect that the proposed technique can out perform existing techniques.

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