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CAD-Directed SEU Susceptibility Reduction in FPGA Circuits Designs

H. Zarandi, S. G. Miremadi, Dhiraj Pradhan, Jimson Mathew, CAD-Directed SEU Susceptibility Reduction in FPGA Circuits Designs. IEEE International Conference on Circuits and Systems, (ISCAS 2007), USA. May 2007. No electronic version available.

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