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A novel framework for logic verification in a synthesis environment

Kunz, W. , Dhiraj Pradhan, Reddy, S.M. , A novel framework for logic verification in a synthesis environment. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, , 15(1). ISBN 0278-0070 , pp. 20–32. January 1996. PDF, 1473 Kbytes.

Abstract

A new methodology for formal logic verification of combinational circuits is presented. Specifically, a structural (logic network) approach is used, based on indirect implications derived by recursive learning. It is shown that implications can be used to capture similarity between designs. This is extended to formulate a hybrid approach, this structural (logic network) information is used to reduce the complexity of a subsequent functional method based on OBDDs. We demonstrate that OBDD-based verification can take great advantage of structural preprocessing in a synthesis environment where many small operations are performed that modify the circuit. The experimental results show that an effective combination can be achieved between memory efficient structural methods and powerful functional methods

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