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Using Media Processors for Low-Memory AES Implementation

D. Page, J. Irwin, Using Media Processors for Low-Memory AES Implementation. 14th International Conference on Application-specific Systems, Architectures and Processors (ASAP). E. Deprettere, S. Bhattacharyya, J. Cavallaro, A. Darte, L. Thiele , (eds.). ISBN 0-7695-1992-X, pp. 144–154. June 2003. No electronic version available.

Abstract

Most performance studies of AES make traditional space versus time trade-offs by allowing large look-up tables to accelerate operations that would normally be calculated by the processor. However, AES is a versatile algorithm and can also be optimised for low-memory use in constrained environments. In this paper we investigate the possibility of getting the best of both worlds -- an application specific hardware and software solution that has a low dependency on memory yet still executes fast enough to consider for use in production systems. The resulting software is attractive in high level design since it allows AES to be more easily deployed as a composable element in larger systems and scale better as processor speed increases.

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