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Predictable Instruction Caching for Media Processors

J. Irwin, D. May, H. L. Muller, D. Page, Predictable Instruction Caching for Media Processors. 13th International Conference on Application-specific Systems, Architectures and Processors (ASAP). M. Shulte, S. Bhattacharyya, N. Burgess, R. Schreiber, (eds.). ISBN 0-7695-1712-9, pp. 141–150. July 2002. PDF, 70 Kbytes.

Abstract

The determinism of instruction cache performance can be considered a major problem in multi-media devices which hope to maximise their quality of service. If instructions are evicted from the cache by competing blocks of code, the running application will take significantly longer to execute than if the instructions were present. Since it is difficult to predict when this interference will occur, the performance of the algorithm at a given point in time is unclear. We propose the use of an automatically configured partitioned cache to protect regions of the application code from each other and hence minimise interference. As well as being specialised to the purpose of providing predictable performance, this cache can be specialised to the application being run, rather than for the average case, using simple compiler algorithms.

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