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Microcomputer with interrupt packets

David May, Andrew Jones, Microcomputer with interrupt packets. Patent. EP953913. November 1999. No electronic version available. External information


An integrated circuit device (11) has an address and data path (15) interconnecting a CPU (12) with modules (14) the modules having event logic (8) to generate an event request packet having a destination address and the CPU decoding the packet to selectively respond to the request of the packet depending on the priority of the event

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