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Microcomputer with bit packets for interrupts, control and memory access

David May, Andrew Jones, Microcomputer with bit packets for interrupts, control and memory access. Patent. EP953914. November 1999. No electronic version available. External information

Abstract

A computer system comprises one or more chips (11) each having at least one CPU (12) interconnected by an address and data path (15) to a plurality of modules (14) and an external communication port (30) the address and data path (15) distributing between devices bit packets comprising memory access packets, event packets for prioritised interrupts and control packets for control commands each of the packets being formed selectively in response to both software and hardware circuitry and having a common format including destination address and decodable function.

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