Skip to main content

Microcomputer with packet translation for event packets and memory access packets

David May, Andrew Jones, Microcomputer with packet translation for event packets and memory access packets. Patent. EP953915. November 1999. No electronic version available. External information

Abstract

A chip (11) with an address and data path (15) interconnecting at least one CPU (12) with another module (14) and an external communication port (30), the CPU generating event packets and memory access packets and the module (14) generating event packets, the packets being distributed in parallel format on the path 15 and the external communication port (30) including circuitry to reduce the parallel format of each packet to a more serial format for off-chip communication.

Bibtex entry.

Contact details

Publication Admin