The aim of this work is the development and application of a partial evaluation procedure for rewriting-based functional logic programs. Functional logic programming languages unite the two main declarative programming paradigms. The rewriting-based computational model extends traditional functional programming languages by incorporating logical features, including logical variables and built-in search, into its framework. This work is the first to address the automatic specialisation of these functional logic programs. In particular, a theoretical framework for the partial evaluation of rewriting-based functional logic programs is defined and its correctness is established. Then, an algorithm is formalised which incorporates the theoretical framework for the procedure in a fully automatic technique. Constraint solving is used to represent additional information about the terms encountered during the transformation in order to improve the efficiency and size of the residual programs. Experiments using an implementation of the algorithm for the partial evaluation of Escher programs show that the specialiser not only passes the ``KMP-test'', but also can perform the elimination of data structures and obtains notable speed-up for McCarthy's 91-function. Circuit simulation lends itself to optimisation by partial evaluation. A general interpreted-code circuit simulator can be specialised with respect to a particular design in order to improve the simulation speed. In this work, a simulator is implemented for behavioural and register-transfer level designs written in the Verilog hardware description language. Testing and verification of high-level designs using interpreted-code simulators is notoriously inefficient. In this thesis, it is shown that the efficiency of an event-driven simulator for behavioural or register-transfer level designs can be improved automatically by partial evaluation.