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Parallel Calibrated Emulation as a Technique for Evaluating Parallel Architectures

Henk L. Muller, Sanjay Raina, Paul W. A. Stallard, David H. D. Warren, Parallel Calibrated Emulation as a Technique for Evaluating Parallel Architectures. Computer systems science and engineering, 13 (1). ISSN 0267-6192, pp. 125–133. January 1998. PDF, 129 Kbytes.

Abstract

We describe the use of a calibrated emulator to simulate a parallel computer architecture. The emulator has a virtual clock, but unlike the virtual clock of a simulator, the emulator clock is bound to a fixed fraction of real time. Individual processors time actions independently, thus without the need for a globally synchronised clock value. Each component of the emulator is calibrated (by slowing it down artificially) so that the balance of the speeds of all components reflects the balance of the system under consideration. Unlike an ordinary simulator, a calibrated emulator is \em inherently parallel. The technique has been applied in the form of a parallel transputer-based emulator developed to evaluate the DDM---a scalable virtual shared memory architecture. The emulator provides performance results of a hardware implementation of the DDM using a calibrated virtual clock. A large transputer platform is used to run experiments. A couple of hours are sufficient to emulate the execution of a realistic application on a large DDM.

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