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Parallel Evaluation of a Parallel Architecture by means of Calibrated Emulation

Henk L. Muller, Paul W. A. Stallard, David H. D. Warren, Sanjay Raina, Parallel Evaluation of a Parallel Architecture by means of Calibrated Emulation. Proceedings of the 8th International Parallel Processing Symposium. ISBN 0-8186-5602-6, pp. 260–267. April 1994. PDF, 80 Kbytes.

Abstract

A parallel transputer-based emulator has been developed to evaluate the DDM---a highly parallel virtual shared memory architecture. The emulator provides performance results of a hardware implementation of the DDM using a calibrated virtual clock. Unlike the virtual clock of a simulator, the emulator clock is bound to a fixed fraction of real time so individual processors may time actions independently without the need for a global clock value. Each component of the emulator is artificially slowed down so that the balance of the speeds of all components reflects the balance of the expected hardware implementation. The calibrated emulator runs an order of magnitude faster than a simulator (the application program is executed directly and there is no overhead for the maintenance of event lists) and more importantly, the emulator is inherently parallel. This results in a peak emulation speed of 16 million instructions per second when simulating a machine with 81 leaf nodes on a 121 node transputer system.

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