Publications by Jimson Mathew

This is a list of all publications (co-)authored by Jimson Mathew that are contained in the publications database of the Department of Computer Science, University of Bristol. To perform an alternative search of the publications database, please go to the publications database home page.

2013

Mike Huang, Jimson Mathew, Rishad Shafik, Subhasis Bhattacharjee, Dhiraj Pradhan, A Fast and Effective DFT for Test and Diagnosis of Power Switches in SOCs. Design, Automation, and Test in Europe (DATE) Conference. February 2013. No electronic version available.
Jimson Mathew, S.P.Mohanty, Dhiraj Pradhan, Attack Tolerant Cryptographic Hardware Design by Combining Error Correction and Uniform Switching Activity. Elsevier Journal of Electrical and Computer Engineering, . January 2013. No electronic version available.

2012

Galadanci, J, Shafik, R.A, Jimson Mathew, Dhiraj Pradhan, A Closed-loop Control Strategy for Glucose Control in Artificial Pancreas Systems. In: IEEE Computer Society Intl. Symposium on Electronic Systems Design. October 2012. No electronic version available.
M. Poolakkaparambil, Jimson Mathew, A. M. Jabir, S. P. Mohanty, “Low Complexity Cross Parity Codes for Multiple and Random Bit Error Correction. 11th IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 141–146. September 2012. No electronic version available.
Jimson Mathew, Patra P., Dhiraj Pradhan, Kuttyamma, A.J, Eco-friendly Computing and Communication Systems. . ISBN 978-3-642-32111-5. August 2012. No electronic version available.
Narayanan, V.K, Shafik, R.A, Jimson Mathew, Dhiraj Pradhan, Fault Tolerant High Performance Galois Field Arithmetic Processor. Lecture Notes in Computer Science, . August 2012. No electronic version available.
H Rahaman, Jimson Mathew, A. M. Jabir, Dhiraj Pradhan, VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF(2m)Using Dual Bases . Lecture note in Computer Science (LNCS) , Springer. ISSN 0302-9743, pp. 258–269. July 2012. No electronic version available.
R. A. Shafik, B. M. Al-Hashimi, Jimson Mathew, Dhiraj Pradhan, S. P. Mohanty, RAEF: A Power Normalized System-Level Reliability Analysis and Estimation Framework. 1th IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 189–194. June 2012. No electronic version available.
P. Yeolekar, R. A. Shafik, Jimson Mathew, Dhiraj Pradhan, S. P. Mohanty, “STEP: A Unified Design Methodology for Secure Test and IP Core Protection. 21st ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), , 2012 , pp. 333–338. May 2012. No electronic version available.
M. Poolakkaparambil,, Jimson Mathew, A. M. Jabir, S. P. Mohanty, Low Complexity Cross Parity Codes for Multiple and Random Bit Error Correction. 13th IEEE International Symposium on Quality Electronic Design (ISQED), pp. 57–62. March 2012. No electronic version available.
L. Sun,, Jimson Mathew, Dhiraj Pradhan, S. P. Mohanty, “Enhanced Statistical Blockade Approaches for Fast Robustness Estimation and Compensation of Nano-CMOS Circuits. Journal of Low Power Electronics (JOLPE), 8(3), pp. 261–269. January 2012. No electronic version available.

2011

V. Mishra, L. C. Tong , S. Chan, Jimson Mathew, MAC Protocol for Two Level QoS Support in Cognitive Radio Network. IEEE, International Symposium on Electronic System Design (ISED), 2011 , pp. 296–301. December 2011. No electronic version available.
Hosseinabady, M, Jimson Mathew, Mohanty, Dhiraj Pradhan, Single-Event Transient Analysis in High Speed Circuits. International Symposium on Electronic System Design (ISED), 2011 , pp. 112–117. December 2011. No electronic version available.
Luo Sun, Jimson Mathew, Dhiraj Pradhan, Saraju Mohanty, Statistical Blockade Method for Fast Robustness Estimation and Compensation of Nano-CMOS Arithmetic Circuits. IInternational Symposium on Electronic System Design (ISED), , pp. 194–1999. December 2011. No electronic version available.
S. Banerjee, Jimson Mathew, S.P. Mohanty, Dhiraj Pradhan, M. Ciesielski, A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization. Journal of Low Power Electronics, 7(4), pp. 471–481. December 2011. No electronic version available.
M. Hosseinabady, R. Kakoee, Jimson Mathew, Dhiraj Pradhan, Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn Graph. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 99, pp. 1469 –1480. September 2011. PDF, 2054 Kbytes.
V. Misra, Jimson Mathew, Dhiraj Pradhan, Fault-tolerant De-Bruijn Graph Based Multipurpose Architecture and Routing Protocol for WSN. International Journal of Sensor Networks (IJSNet), . May 2011. No electronic version available.
Jimson Mathew, K. Maharatna, Dhiraj Pradhan, Pseudo-parallel Datapath Structure for Power Optimal Implementation of 128-pt FFT/IFFT for Wireless Personal Area Networks. Circuits, Systems, and Signal Processing, . ISBN ISSN: 0278-081X. April 2011. No electronic version available.
Mahesh P., Jimson Mathew, A.M. Jabir, Dhiraj Pradhan, S. P. Mohanty, BCH Code Based Multiple Bit Error Correction in Finite Field Multiplier Circuits. Proceedings of the 12th IEEE International Symposium on Quality Electronic Design (ISQED),. ISSN 29696771. March 2011. No electronic version available.
S. Banerjee, Jimson Mathew, Dhiraj Pradhan, A Routing-Aware ILS Design Technique. at IEEE Transactions on Very Large Scale Integration Systems , . ISSN 1063-8210. March 2011. No electronic version available.
S. Banerjee, Jimson Mathew, Dhiraj Pradhan, S.P. Mohanty, Variation-Aware TED- Based Approach for Nano-CMOS RTL Leakage Optimization. IEEE 24th International Conference on VLSI Design. ISSN 1063-8210. January 2011. No electronic version available.

2010

Jimson Mathew, P. Mahesh, A.M. Jabir, Dhiraj Pradhan, Multiple bits Error Detection and Correction in GF Arithmetic Circuits. International Symposium on Electronic System Design (ISED). December 2010. No electronic version available.
Anas Abu Taleb, Jimson Mathew, Dhiraj Pradhan, Efficient Fault Tolerant De Bruijn Based Design Approach for Sensor Networks. 4^th International Conference on Sensor Technologies and Applications, 2010. SENSORCOMM , Italy. July 2010. No electronic version available.
H. Rahaman, Jimson Mathew, A. Jabir, Dhiraj Pradhan, Simplified Bit Parallel Systolic Multipliers for Special Class of GF(2m) with Testability. IET Computers and Digital Techniques, . July 2010. No electronic version available.
Anas Abu Taleb, Jimson Mathew, Dhiraj Pradhan, Fault Diagnosis in Multi Layered De Bruijn Based Architectures for Sensor Networks. 6^th IEEE Int Workshop on Sensor Networks and Systems for Pervasive computing((PerSeNs 2010). June 2010. No electronic version available.
Luo Sun, Jimson Mathew, Dhiraj Pradhan, S. P. Mohanty, Algorithms for Rare Event Analysis in Nano-CMOS Circuits Using Statistical Blockade. Proceedings of the International SoC Design Conference (ISOCC). May 2010. No electronic version available.
Anas Abu Taleb, Jimson Mathew, Dhiraj Pradhan, Clustered De Bruijn Multi Layered Architectures for Sensor Networks. Lecture notes in Computer Science. April 2010. No electronic version available.
Jimson Mathew, Dhiraj Pradhan, On the Design of Different Concurrent EDC Schemes for S-box and GF(P)",. Proceedings of the 11th IEEE International Symposium on Quality Electronic Design (ISQED). March 2010. No electronic version available.
Anas Abu Taleb, Jimson Mathew, Dhiraj Pradhan, A Novel Fault Diagnosis Technique in Wireless Sensor Networks. The International Journal On Advances in Networks and Services, . March 2010. No electronic version available.
Jimson Mathew, A Jabir, A.K Singh, H.Rahaman, Dhiraj Pradhan, A Galois Field Based Logic Synthesis Approach with Testability. IET Computers & Digital Techniques, . March 2010. No electronic version available.

2009

Jimson Mathew, A. M. Jabir, H. Rahaman, Dhiraj Pradhan, Single Error Correctable Bit Parallel Multipliers Over GF(2^m). IET Computers & Digital Techniques, . December 2009. No electronic version available.
H. Rahaman, Jimson Mathew, Dhiraj Pradhan, Test Generation in Systolic Architecture for Multiplication over GF(2^m). IEEE Transactions on VLSI Systems, . November 2009. No electronic version available.
H Rahaman, Jimson Mathew, Dhiraj Pradhan, C-testable S-box Implementation for Secure Advanced Encryption Standard. IEEE International Online Test Syposium (IOLTS 2009). July 2009. No electronic version available.
D. Maslov, Jimson Mathew, D. Cheung, Dhiraj Pradhan, AN O(m2)-DEPTH QUANTUM ALGORITHM FOR THE ELLIPTIC CURVE DISCRETE LOGARITHM PROBLEM OVER GF(2^m). Journal of Quantum Information & Computation, 9(7), pp. 0610–0627. July 2009. No electronic version available.
A.K Singh, A Bera, H. Rahaman, Jimson Mathew, Dhiraj Pradhan, Error Tolerant Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m),. International Journal of Electronic Science and Technology, . July 2009. No electronic version available.
Jimson Mathew, A Jabir, H. Rahaman, Costas Argyrides, Dhiraj Pradhan, On the Synthesis of Bit-Parallel Galois Field Multipliers with On-line SEC and DED. , . July 2009. No electronic version available.
H. Rahaman, Jimson Mathew, A. K Singh, Dhiraj Pradhan, Transition Fault Detection in Bit Parallel Multipliers over GF(2^m). Transactions on Circuits and Systems, . May 2009. No electronic version available.
H. Rahaman, Jimson Mathew, Dhiraj Pradhan, Secure Testable S-box Architecture for Cryptographic Hardware Implementation. The Computer Journal, . April 2009. No electronic version available.
J Singh, D K Pradhan, S Hollis, S P Mohanty, J Mathew, Single Ended 6T SRAM with Isolated Read-Port for Low-Power Embedded Systems. 12th IEEE International Conference on Design Automation and Test in Europe (DATE), 2009. April 2009. No electronic version available.
Jawar Singh, Jimson Mathew, S. P. Mohanty, Dhiraj Pradhan, Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems. IEEE International Conference on VLSI Design, pp. 307–312. February 2009. No electronic version available.

2008

Jimson Mathew, R. Mahesh, A.P Vinod, L. Edmund, Realization of Low Power High-Speed Channel Filters with Stringent Adjacent Channel Attenuation. IEICE Trasactions, . December 2008. No electronic version available.
Jawar Singh, Jimson Mathew, Dhiraj Pradhan, Failure Analysis for Ultra Low Power Nano-CMOS SRAM Under Process Variations. IEEE International System On Chip Conference (SOCC’ 2008). . September 2008. No electronic version available.
M. Hosseinabady, R. Kakoee, Jimson Mathew, Dhiraj Pradhan, De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs. Proceedings of the conference on Design, automation and test in Europe (DATE 2008), pp. 1370–1273. August 2008. PDF, 142 Kbytes.
H. Rahaman, Jimson Mathew, Dhiraj Pradhan, Derivation of Reduced Test Vectors for Bit Parallel Multipliers over GF(2^m). IEEE Transactions on Computers , . August 2008. No electronic version available.
A. M. Jabir, Dhiraj Pradhan, Jimson Mathew, GfXpress: A Technique for Synthesis and Optimization of GF(2^m )Polynomials. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, , 27(4). ISSN 0278-0070, pp. 698–711. April 2008. PDF, 657 Kbytes.
Jimson Mathew, Costas Argyrides, A. Jabir, Dhiraj Pradhan, Single Error Correcting Finite Field Multipliers over GF(2m). 21st Conference on VLSI Design VLSI 08. January 2008. No electronic version available.
H. Rahaman, Jimson Mathew, Dhiraj Pradhan, A. M. Jabir, C-Testable Bit Parallel Multipliers Over GF(2m). ACM Transactions on Design Automation of Electronic Systems (TODAES), . January 2008. No electronic version available.

2007

M. Hosseinabady, M. Reza, Jimson Mathew, Dhiraj Pradhan, Reliable Network-on-Chip Based on Generalized de Bruijn Graph. IEEE International High Level Design Validation and Test Workshop (HLDVT) (to appear). November 2007. No electronic version available.
B. R. Jose, Jimson Mathew, P. Mythili, Dhiraj Pradhan, A Triple-Mode Feed-Forward Sigma-Delta Modulator Design For GSM / WCDMA / WLAN Applications. 20th IEEE International System On Chip Conference (IEEE SOCC 2007), September 2007. . September 2007. No electronic version available.
Jimson Mathew, H. Rahaman, Dhiraj Pradhan, Efficient Testable Bit Parallel Multipliers over GF(2^m) with Constant Test Set. 13th IEEE International On-Line Testing Symposium,Greece. June 2007. No electronic version available.
H. Zarandi, S. G. Miremadi, Dhiraj Pradhan, Jimson Mathew, CAD-Directed SEU Susceptibility Reduction in FPGA Circuits Designs. IEEE International Conference on Circuits and Systems, (ISCAS 2007), USA. May 2007. No electronic version available.
H. Zarandi, S. G. Miremadi, Dhiraj Pradhan, Jimson Mathew, Soft Error Mitigation in Switch Modules of SRAM-Based FPGAs. IEEE International Conference on Circuits and Systems, (ISCAS 2007), USA. May 2007. No electronic version available.
R. Stapenhurst, Koushik Maharatna, Jimson Mathew, J. Nunez-Yanez, Dhiraj Pradhan, On the Hardware Reduction of z-Datapath of Vectoring CORDIC. IEEE International Conference on Circuits and Systems, (ISCAS 2007), USA. May 2007. No electronic version available.
M. Hosseinabady, Jimson Mathew, Dhiraj Pradhan, Application of de Bruijn graphs to NoC design. Design Automation and Test in Europe Workshops, DATE07-WKS , pp. 111–116. March 2007. No electronic version available.
H. Rahaman, Jimson Mathew, Dhiraj Pradhan, Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m). Chapter in VLSI Design, 2007, pp. 479–484. January 2007. No electronic version available.

2006

A. Jabir, Dhiraj Pradhan, Jimson Mathew, An Efficient Technique for Synthesis and Optimization of Polynomials in GF(2m). IEEE International Conference on Computer Aided Design. ISBN 1-59593-389-1, pp. 151–157. November 2006. No electronic version available.
H. Rahaman, Jimson Mathew, Dhiraj Pradhan, A.M. Jabir, Easily Testable Implementation for Bit Parallel Multipliers in GF(2m). IEEE International High Level Design Validation and Test Workshop(HLDVT). November 2006. No electronic version available.
Costas Argyrides, Jimson Mathew, Ahmad Al-Yamani, Dhiraj Pradhan, Performance Analysis of an Error Tolerant Low Power Memory Architecture. IEEE International Design and Test Workshop. November 2006. PDF, 333 Kbytes.
Jimson Mathew, Koushik Maharatna, Dhiraj Pradhan, A Low Power 128-Pt Implementation of FFT/IFFT for High Performance Wireless Personal Area Networks. IEEE PRIME Conference, pp. 377–380. June 2006. No electronic version available.
Jimson Mathew, Koushik Maharatna, Dhiraj Pradhan, Exploration of Power optimal Implementation Technique of 128-Pt FFT/IFFT for WPAN using Pseudo- Parallel Datapath Strcuture. IEEE International Conference on Communication Systems, Singapore. February 2006. No electronic version available.