@inproceedings{2001328,
author={Stefan Tillich and  Martin Feldhofer and  Mario Kirschbaum and  Thomas Plos and  Jörn-Marc Schmidt and Alexander Szekely},
title={Hardware Implementations of the Round-Two SHA-3 Candidates: Comparison on a Common Ground},
booktitle={Proceedings of Austrochip 2010, Villach, Austria, October 6, 2010},
ISBN={978-3-200-01945-4},
publisher={Fachhochschule Kärnten},
pages={43--48},
month={October},
year={2010},
abstract={Hash functions are a core part of many protocols that are in daily use. Following recent results that raised concerns regarding the security of the current hash standards, the
National Institute of Standards and Technology (NIST) pronounced a competition to find a new Secure Hash Algorithm (SHA), the SHA-3. An important criterion for the new standard is not only its security, but also the performance and the costs of its implementations.
This paper evaluates all 14 candidates that are currently in the second round of the SHA-3 competition. We provide a common framework that allows a fair comparison of the hardware implementations of all SHA-3 candidates. We optimized the hardware modules
towards maximum throughput and give concrete numbers of our implementations for a 0.18 μm standard-cell technology.},
abstract-url={http://www.cs.bris.ac.uk/Publications/pub_master.jsp?id=2001328},
url={http://www.cs.bris.ac.uk/Publications/Papers/2001328.pdf},
keyword={Cryptography},
pubtype={102}
}